← ai corner add1_flow add1 old 5-core hardware/state dependency trace cluster_old_brisc brisc cluster_old_trisc0 trisc0 cluster_old_trisc1 trisc1 cluster_old_trisc2 trisc2 cluster_old_ncrisc ncrisc legend_top semaphore CB / dataflow NOC mailbox MOP / replay SFPU math config / MMIO pack / unpack sync / stall old_brisc_0 000  brisc  00004b90  lw NOC1.niu_mst_rd_resp_received t4 <- NOC1.niu_mst_rd_resp_received old_trisc0_0 000  trisc0  00005ec4  sw add1.TRISC0_UNP_CFG_CONTEXT zero=0x00000000 old_trisc1_0 000  trisc1  000062a8  sw TriscCB[0].num_pages zero=0x00000000 old_trisc2_0 000  trisc2  00006aac  sw add1.TRISC0_UNP_CFG_CONTEXT zero=0x00000000 old_ncrisc_0 000  ncrisc  000059b0  lw NOC0.niu_mst_rd_resp_received a4 <- NOC0.niu_mst_rd_resp_received old_brisc_1 001  brisc  00004b94  lw NOC1.niu_mst_nonposted_wr_req_sent t1 <- NOC1.niu_mst_nonposted_wr_req_sent old_brisc_0->old_brisc_1 old_brisc_2 002  brisc  00004b98  lw NOC1.niu_mst_wr_ack_received a0 <- NOC1.niu_mst_wr_ack_received old_brisc_1->old_brisc_2 old_brisc_3 003  brisc  00004b9c  lw NOC1.niu_mst_atomic_resp_received a1 <- NOC1.niu_mst_atomic_resp_received old_brisc_2->old_brisc_3 old_brisc_4 004  brisc  00004ba0  lw NOC1.niu_mst_posted_wr_req_sent a2 <- NOC1.niu_mst_posted_wr_req_sent old_brisc_3->old_brisc_4 old_brisc_5 005  brisc  00004ba4  lw TensixL1.GO_MSG_INDEX a4 <- TensixL1.GO_MSG_INDEX old_brisc_4->old_brisc_5 old_brisc_6 006  brisc  00004bfc  lw BM.RTA_L1_BASE_PTR a5 <- BM.RTA_L1_BASE_PTR old_brisc_5->old_brisc_6 old_brisc_7 007  brisc  00004c54  lw CB_SYNC.tiles_acked[16] a3 <- CB_SYNC.tiles_acked[16] old_brisc_6->old_brisc_7 old_brisc_8 008  brisc  00004c5c  lw CB_SYNC.tiles_received[16] a5 <- CB_SYNC.tiles_received[16] old_brisc_7->old_brisc_8 old_brisc_9 009  brisc  00004c88  lw BriscCB[16].rd_ptr s1 <- BriscCB[16].rd_ptr old_brisc_8->old_brisc_9 old_brisc_10 010  brisc  00004c94  lw NOC1.noc_cmd_ctrl[buf0] a5 <- NOC1.noc_cmd_ctrl[buf0] old_brisc_9->old_brisc_10 old_brisc_11 011  brisc  00004c9c  sw NOC1.noc_ctrl[buf0] t4=0x00002092 old_brisc_10->old_brisc_11 old_brisc_12 012  brisc  00004ca0  sw NOC1.noc_targ_addr_lo[buf0] s1=unknown old_brisc_11->old_brisc_12 old_brisc_13 013  brisc  00004ca4  sw NOC1.noc_ret_addr_lo[buf0] a3=unknown old_brisc_12->old_brisc_13 old_brisc_14 014  brisc  00004ca8  sw NOC1.noc_ret_addr_mid[buf0] zero=0x00000000 old_brisc_13->old_brisc_14 old_brisc_15 015  brisc  00004cb8  sw NOC1.noc_ret_addr_hi[buf0] a5=unknown old_brisc_14->old_brisc_15 old_brisc_16 016  brisc  00004cbc  sw NOC1.noc_at_len_be[buf0] t3=0x00000800 old_brisc_15->old_brisc_16 old_brisc_17 017  brisc  00004cc0  sw NOC1.noc_cmd_ctrl[buf0] t0=0x00000001 old_brisc_16->old_brisc_17 old_brisc_18 018  brisc  00004cd4  lw NOC1.niu_mst_wr_ack_received a5 <- NOC1.niu_mst_wr_ack_received old_brisc_17->old_brisc_18 old_brisc_19 019  brisc  00004ce0  lw CB_SYNC.tiles_acked[16] a3 <- CB_SYNC.tiles_acked[16] old_brisc_18->old_brisc_19 old_brisc_20 020  brisc  00004ce4  lw BriscCB[16].rd_ptr s0 <- BriscCB[16].rd_ptr old_brisc_19->old_brisc_20 old_brisc_21 021  brisc  00004ce8  lw BriscCB[16].page_size a5 <- BriscCB[16].page_size old_brisc_20->old_brisc_21 old_brisc_22 022  brisc  00004cf4  lw BriscCB[16].fifo_limit s0 <- BriscCB[16].fifo_limit old_brisc_21->old_brisc_22 old_brisc_23 023  brisc  00004cf8  sw CB_SYNC.tiles_acked[16] a3=unknown old_brisc_22->old_brisc_23 old_brisc_24 024  brisc  00004cfc  sw BriscCB[16].rd_ptr a5=unknown old_brisc_23->old_brisc_24 old_trisc2_80 080  trisc2  00006df8  lw CB_SYNC.tiles_acked[16] a4 <- CB_SYNC.tiles_acked[16] old_brisc_23->old_trisc2_80 old_brisc_25 025  brisc  00004d04  lw BriscCB[16].fifo_size a3 <- BriscCB[16].fifo_size old_brisc_24->old_brisc_25 old_brisc_26 026  brisc  00004d0c  sw BriscCB[16].rd_ptr a5=unknown old_brisc_24->old_brisc_26 old_brisc_25->old_brisc_26 old_trisc0_1 001  trisc0  00005f34  sw add1.TRISC0_UNP_CFG_CONTEXT a0=unknown old_trisc0_0->old_trisc0_1 old_trisc0_32 032  trisc0  0000609c  sw tensix_cfg+0x4d0 a1=0x00400040 | bank1.cfg[84] value: THCON_SEC0_REG5_Dest_cntx0_address=64, THCON_SEC0_REG5_Dest_cntx1_address=64 old_trisc0_2 002  trisc0  00005f64  sw riscv_debug_regs.dbg_feature_disable zero=0x00000000 old_trisc0_1->old_trisc0_2 old_trisc0_42 042  trisc0  000060f4  sw add1.TRISC0_UNP_CFG_CONTEXT zero=0x00000000 old_trisc0_1->old_trisc0_42 old_trisc0_3 003  trisc0  00005f68  lw TensixL1.GO_MSG_INDEX a4 <- TensixL1.GO_MSG_INDEX old_trisc0_2->old_trisc0_3 old_trisc0_4 004  trisc0  00005f8c  tensix Tensix instruction ttzerosrc 0,0,1,3 old_trisc0_3->old_trisc0_4 old_trisc0_5 005  trisc0  00005f94  lw TM.DATA1['my_logical_y'] a5 <- TM.DATA1['my_logical_y'] old_trisc0_4->old_trisc0_5 old_trisc0_6 006  trisc0  00005fa4  lw TriscCB[0].page_size a3 <- TriscCB[0].page_size old_trisc0_5->old_trisc0_6 old_trisc0_7 007  trisc0  00005fac  lw add1.TENSIX_PC_UNPACK_SYNC a5 <- add1.TENSIX_PC_UNPACK_SYNC (PC_BUF_SEM[5]) old_trisc0_6->old_trisc0_7 old_trisc0_8 008  trisc0  00005fb8  tensix Tensix instruction ttsetadcxy 3,0,0,0,0,11 | addr_counter XY ch0=(0,0) ch1=(0,0) mask=0xb old_trisc0_7->old_trisc0_8 old_trisc0_9 009  trisc0  00005fbc  tensix Tensix instruction ttsetadczw 3,0,0,0,0,15 | addr_counter ZW ch0=(0,0) ch1=(0,0) mask=0xf old_trisc0_8->old_trisc0_9 old_trisc0_10 010  trisc0  00005fc4  lw TM.LOCAL_END[1] a4 <- TM.LOCAL_END[1] old_trisc0_9->old_trisc0_10 old_trisc0_11 011  trisc0  00005fd8  sw tensix_cfg+0x464 a4=0x00000200 | bank1.cfg[57] value: UNP0_ADDR_CTRL_ZW_REG_1_Zstride=512, UNP0_ADDR_CTRL_ZW_REG_1_Wstride=0 old_trisc0_10->old_trisc0_11 old_trisc0_12 012  trisc0  00005fdc  sw tensix_cfg+0x46c a4=0x00000200 | bank1.cfg[59] value: UNP1_ADDR_CTRL_ZW_REG_1_Zstride=512, UNP1_ADDR_CTRL_ZW_REG_1_Wstride=0 old_trisc0_11->old_trisc0_12 old_trisc0_13 013  trisc0  00005fe0  tensix Tensix instruction ttatgetm 0 old_trisc0_12->old_trisc0_13 old_trisc0_14 014  trisc0  00005ff0  tensix Tensix instruction a4=TTRMWCIB0(0xFF) old_trisc0_13->old_trisc0_14 old_trisc0_15 015  trisc0  00005ff8  tensix Tensix instruction a4=TTRMWCIB1(0x7F) old_trisc0_14->old_trisc0_15 old_trisc0_14->old_trisc0_15 tensix_instr old_trisc0_16 016  trisc0  00006004  tensix Tensix instruction a4=TTRMWCIB0(7, 0, 1) old_trisc0_15->old_trisc0_16 old_trisc0_15->old_trisc0_16 tensix_instr old_trisc0_17 017  trisc0  00006010  tensix Tensix instruction a4=TTRMWCIB1(0x80, 0, 1) old_trisc0_16->old_trisc0_17 old_trisc0_16->old_trisc0_17 tensix_instr old_trisc0_18 018  trisc0  0000601c  tensix Tensix instruction a4=TTRMWCIB2(1, 0, 1) old_trisc0_17->old_trisc0_18 old_trisc0_17->old_trisc0_18 tensix_instr old_trisc0_19 019  trisc0  00006028  tensix Tensix instruction a4=TTRMWCIB3(0x60, 0, 1) old_trisc0_18->old_trisc0_19 old_trisc0_18->old_trisc0_19 tensix_instr old_trisc0_20 020  trisc0  00006034  tensix Tensix instruction a4=TTRMWCIB0(1, 1, 2) old_trisc0_19->old_trisc0_20 old_trisc0_19->old_trisc0_20 tensix_instr old_trisc0_21 021  trisc0  00006038  tensix Tensix instruction ttatrelm 0 old_trisc0_20->old_trisc0_21 old_trisc0_30 030  trisc0  00006084  tensix Tensix instruction a4=TTSETADCXX(1, 0xFF) old_trisc0_20->old_trisc0_30 tensix_instr old_trisc0_22 022  trisc0  00006040  sw tensix_cfg+0x480 a4=0x00000015 | bank1.cfg[64] value: THCON_SEC0_REG0_TileDescriptor=21 old_trisc0_21->old_trisc0_22 old_trisc0_23 023  trisc0  00006050  sw tensix_cfg+0x484 a4=0x00040001 old_trisc0_22->old_trisc0_23 old_trisc0_24 024  trisc0  00006058  sw tensix_cfg+0x540 a1=0x01000015 | bank1.cfg[112] value: THCON_SEC1_REG0_TileDescriptor=16777237 old_trisc0_23->old_trisc0_24 old_trisc0_25 025  trisc0  0000605c  sw tensix_cfg+0x544 a4=0x00040001 old_trisc0_24->old_trisc0_25 old_trisc0_26 026  trisc0  00006068  sw tensix_cfg+0x4a0 a1=0x00000025 | bank1.cfg[72] value: THCON_SEC0_REG2_Out_data_format=5, THCON_SEC0_REG2_Throttle_mode=2,... old_trisc0_25->old_trisc0_26 old_trisc0_27 027  trisc0  00006070  sw tensix_cfg+0x4a4 a4=0x000f000f | bank1.cfg[73] value: THCON_SEC0_REG2_Disable_zero_compress_cntx0=1, THCON_SEC0_REG2_Disable_zero_compress_cntx1=1,... old_trisc0_26->old_trisc0_27 old_trisc0_28 028  trisc0  00006074  sw tensix_cfg+0x560 a1=0x00000025 | bank1.cfg[120] value: THCON_SEC1_REG2_Out_data_format=5, THCON_SEC1_REG2_Throttle_mode=2,... old_trisc0_27->old_trisc0_28 old_trisc0_29 029  trisc0  00006078  sw tensix_cfg+0x564 a4=0x000f000f | bank1.cfg[121] value: THCON_SEC1_REG2_Disable_zero_compress_cntx0=1, THCON_SEC1_REG2_Disable_zero_compress_cntx1=1,... old_trisc0_28->old_trisc0_29 old_trisc0_29->old_trisc0_30 old_trisc0_31 031  trisc0  00006094  tensix Tensix instruction a4=TTSETADCXX(2, 0xFF) old_trisc0_30->old_trisc0_31 old_trisc0_30->old_trisc0_31 tensix_instr old_trisc0_31->old_trisc0_32 old_trisc0_44 044  trisc0  00006118  tensix Tensix instruction a3=unknown old_trisc0_31->old_trisc0_44 tensix_instr old_trisc0_33 033  trisc0  000060a4  sw tensix_cfg+0x4d8 a6=0x01000100 | bank1.cfg[86] value: THCON_SEC0_REG5_Tile_x_dim_cntx0=256, THCON_SEC0_REG5_Tile_x_dim_cntx1=256 old_trisc0_32->old_trisc0_33 old_trisc0_64 064  trisc0  000061b0  sw tensix_mop_cfg+0x4 t4=0x00000001 old_trisc0_34 034  trisc0  000060ac  sw tensix_regfile+0xa0 a6=0x01000100 | dma_reg[40] value: lo16=0x0100, hi16=0x0100 old_trisc0_33->old_trisc0_34 old_trisc0_35 035  trisc0  000060b8  sw tensix_regfile+0xa4 a6=0x00800080 | dma_reg[41] value: lo16=0x0080, hi16=0x0080 old_trisc0_34->old_trisc0_35 old_trisc0_36 036  trisc0  000060bc  sw tensix_regfile+0xa8 a1=0x00400040 | dma_reg[42] value: lo16=0x0040, hi16=0x0040 old_trisc0_35->old_trisc0_36 old_trisc0_37 037  trisc0  000060c8  sw tensix_regfile+0xac a1=0x00200020 | dma_reg[43] value: lo16=0x0020, hi16=0x0020 old_trisc0_36->old_trisc0_37 old_trisc0_38 038  trisc0  000060d4  sw tensix_regfile+0xb0 a1=0x00100010 | dma_reg[44] value: lo16=0x0010, hi16=0x0010 old_trisc0_37->old_trisc0_38 old_trisc0_39 039  trisc0  000060dc  lw tensix_regfile+0xb0 a4 <- tensix_regfile+0xb0 (dma_reg[44]) old_trisc0_38->old_trisc0_39 old_trisc0_38->old_trisc0_39 dma_reg:44 old_trisc0_40 040  trisc0  000060e4  tensix Tensix instruction ttsetc16 5,4 | thread_cfg[5] := 0x4 (SRCA_SET) old_trisc0_39->old_trisc0_40 old_trisc0_41 041  trisc0  000060f0  sw tensix_cfg+0x448 a4=0x00000100 | bank1.cfg[50] value: UNP0_FORCED_SHARED_EXP_shared_exp=0, UNP0_ADD_DEST_ADDR_CNTR_add_dest_addr_cntr=1 old_trisc0_40->old_trisc0_41 old_trisc0_41->old_trisc0_42 old_trisc0_43 043  trisc0  000060f8  tensix Tensix instruction ttsetc16 41,0 | thread_cfg[41] := 0x0 (UNPACK_MISC_CFG) old_trisc0_42->old_trisc0_43 old_trisc0_81 081  trisc0  00006244  lw add1.TRISC0_UNP_CFG_CONTEXT a5 <- add1.TRISC0_UNP_CFG_CONTEXT old_trisc0_42->old_trisc0_81 old_trisc0_87 087  trisc0  00006260  sw add1.TRISC0_UNP_CFG_CONTEXT t4=0x00000001 old_trisc0_42->old_trisc0_87 old_trisc0_43->old_trisc0_44 old_trisc0_45 045  trisc0  00006124  tensix Tensix instruction a5=unknown old_trisc0_44->old_trisc0_45 old_trisc0_44->old_trisc0_45 tensix_instr old_trisc0_46 046  trisc0  0000612c  tensix Tensix instruction a6=TTRMWCIB1(1, 0, 0x48) old_trisc0_45->old_trisc0_46 old_trisc0_45->old_trisc0_46 tensix_instr old_trisc0_47 047  trisc0  00006130  tensix Tensix instruction ttsetadcxx 1,255,0 | addr_counter X start=0 end2=255 mask=0x1 old_trisc0_46->old_trisc0_47 old_trisc0_59 059  trisc0  00006190  tensix Tensix instruction a6=TTRMWCIB1(1, 0, 0x48) old_trisc0_46->old_trisc0_59 tensix_instr old_trisc0_48 048  trisc0  00006140  sw add1.TENSIX_PC_BUF_MOP_SYNC a5=unknown old_trisc0_47->old_trisc0_48 old_trisc0_49 049  trisc0  00006144  lw add1.TENSIX_PC_BUF_MOP_SYNC a4 <- add1.TENSIX_PC_BUF_MOP_SYNC (PC_BUF_MOP_SYNC) old_trisc0_48->old_trisc0_49 old_trisc0_48->old_trisc0_49 pcbuf:0x8 old_trisc0_61 061  trisc0  000061a0  sw add1.TENSIX_PC_BUF_MOP_SYNC a6=unknown old_trisc0_48->old_trisc0_61 pcbuf:0x8 old_trisc0_50 050  trisc0  00006158  sw add1.TENSIX_MOP_CFG t5=0x00000004 old_trisc0_49->old_trisc0_50 old_trisc0_51 051  trisc0  00006160  sw tensix_mop_cfg+0x4 t4=0x00000001 old_trisc0_50->old_trisc0_51 old_trisc0_63 063  trisc0  000061ac  sw add1.TENSIX_MOP_CFG t5=0x00000004 old_trisc0_50->old_trisc0_63 mop:0 old_trisc0_52 052  trisc0  00006168  sw tensix_mop_cfg+0x8 a2=0x420080c1 old_trisc0_51->old_trisc0_52 old_trisc0_51->old_trisc0_64 mop:1 old_trisc0_53 053  trisc0  00006170  sw tensix_mop_cfg+0xc a3=0x02000000 old_trisc0_52->old_trisc0_53 old_trisc0_65 065  trisc0  000061b4  sw tensix_mop_cfg+0x8 a2=0x420080c1 old_trisc0_52->old_trisc0_65 mop:2 old_trisc0_54 054  trisc0  00006178  sw tensix_mop_cfg+0x10 a3=0x02000000 old_trisc0_53->old_trisc0_54 old_trisc0_66 066  trisc0  000061b8  sw tensix_mop_cfg+0xc a3=0x02000000 old_trisc0_53->old_trisc0_66 mop:3 old_trisc0_55 055  trisc0  00006180  sw tensix_mop_cfg+0x14 a4=0x43800101 old_trisc0_54->old_trisc0_55 old_trisc0_67 067  trisc0  000061bc  sw tensix_mop_cfg+0x10 a3=0x02000000 old_trisc0_54->old_trisc0_67 mop:4 old_trisc0_56 056  trisc0  00006184  sw tensix_mop_cfg+0x18 a3=0x02000000 old_trisc0_55->old_trisc0_56 old_trisc0_68 068  trisc0  000061c0  sw tensix_mop_cfg+0x14 a4=0x43800101 old_trisc0_55->old_trisc0_68 mop:5 old_trisc0_57 057  trisc0  00006188  sw tensix_mop_cfg+0x1c a4=0x43800101 old_trisc0_56->old_trisc0_57 old_trisc0_69 069  trisc0  000061c4  sw tensix_mop_cfg+0x18 a3=0x02000000 old_trisc0_56->old_trisc0_69 mop:6 old_trisc0_58 058  trisc0  0000618c  sw tensix_mop_cfg+0x20 a4=0x43800101 old_trisc0_57->old_trisc0_58 old_trisc0_70 070  trisc0  000061c8  sw tensix_mop_cfg+0x1c a4=0x43800101 old_trisc0_57->old_trisc0_70 mop:7 old_trisc0_58->old_trisc0_59 old_trisc0_71 071  trisc0  000061cc  sw tensix_mop_cfg+0x20 a4=0x43800101 old_trisc0_58->old_trisc0_71 mop:8 old_trisc0_60 060  trisc0  00006194  tensix Tensix instruction ttsetadcxx 1,255,0 | addr_counter X start=0 end2=255 mask=0x1 old_trisc0_59->old_trisc0_60 old_trisc0_90 090  trisc0  0000627c  tensix Tensix instruction a5=unknown old_trisc0_59->old_trisc0_90 tensix_instr old_trisc0_60->old_trisc0_61 old_trisc0_62 062  trisc0  000061a4  lw add1.TENSIX_PC_BUF_MOP_SYNC a1 <- add1.TENSIX_PC_BUF_MOP_SYNC (PC_BUF_MOP_SYNC) old_trisc0_61->old_trisc0_62 old_trisc0_61->old_trisc0_62 pcbuf:0x8 old_trisc1_27 027  trisc1  000063cc  sw add1.TENSIX_PC_BUF_MOP_SYNC a5=unknown old_trisc0_61->old_trisc1_27 pcbuf:0x8 old_trisc0_62->old_trisc0_63 old_trisc0_63->old_trisc0_64 old_trisc1_29 029  trisc1  000063e4  sw add1.TENSIX_MOP_CFG a1=0x00000004 old_trisc0_63->old_trisc1_29 mop:0 old_trisc0_64->old_trisc0_65 old_trisc0_96 096  trisc0  000062c0  tensix Tensix instruction ttstallwait 8,1024 old_trisc1_30 030  trisc1  000063e8  sw tensix_mop_cfg+0x4 a2=0x00000002 old_trisc0_64->old_trisc1_30 mop:1 old_trisc0_65->old_trisc0_66 old_trisc1_31 031  trisc1  000063f4  sw tensix_mop_cfg+0x8 a1=0x02000000 old_trisc0_65->old_trisc1_31 mop:2 old_trisc0_66->old_trisc0_67 old_trisc1_32 032  trisc1  000063fc  sw tensix_mop_cfg+0xc a2=0x37c00003 old_trisc0_66->old_trisc1_32 mop:3 old_trisc0_67->old_trisc0_68 old_trisc1_33 033  trisc1  00006400  sw tensix_mop_cfg+0x10 a1=0x02000000 old_trisc0_67->old_trisc1_33 mop:4 old_trisc0_68->old_trisc0_69 old_trisc1_34 034  trisc1  00006408  sw tensix_mop_cfg+0x14 a2=0x1200a000 old_trisc0_68->old_trisc1_34 mop:5 old_trisc0_69->old_trisc0_70 old_trisc1_35 035  trisc1  0000640c  sw tensix_mop_cfg+0x18 a1=0x02000000 old_trisc0_69->old_trisc1_35 mop:6 old_trisc0_70->old_trisc0_71 old_trisc1_36 036  trisc1  00006410  sw tensix_mop_cfg+0x1c a2=0x1200a000 old_trisc0_70->old_trisc1_36 mop:7 old_trisc0_72 072  trisc0  000061d4  lw TM.LOCAL_END[1] a4 <- TM.LOCAL_END[1] old_trisc0_71->old_trisc0_72 old_trisc1_37 037  trisc1  00006414  sw tensix_mop_cfg+0x20 a2=0x1200a000 old_trisc0_71->old_trisc1_37 mop:8 old_trisc0_73 073  trisc0  000061f8  lw TriscCB[0].page_size s1 <- TriscCB[0].page_size old_trisc0_72->old_trisc0_73 old_trisc0_74 074  trisc0  000061fc  lw TriscCB[0].fifo_limit s0 <- TriscCB[0].fifo_limit old_trisc0_73->old_trisc0_74 old_trisc0_75 075  trisc0  00006200  lw add1.TRISC1_UNPACK_TILE_NUM_FACES s2 <- add1.TRISC1_UNPACK_TILE_NUM_FACES old_trisc0_74->old_trisc0_75 old_trisc0_76 076  trisc0  00006204  lhu TriscCB[0].tiles_acked_received a4 <- TriscCB[0].tiles_acked_received old_trisc0_75->old_trisc0_76 old_trisc0_77 077  trisc0  00006208  lw TriscCB[0].rd_ptr a1 <- TriscCB[0].rd_ptr old_trisc0_76->old_trisc0_77 old_trisc0_78 078  trisc0  00006224  lw CB.SYNC_TILES_RECEIVED_BASE a5 <- CB.SYNC_TILES_RECEIVED_BASE old_trisc0_77->old_trisc0_78 old_trisc0_79 079  trisc0  00006234  tensix Tensix instruction ttsetadczw 3,0,0,0,0,15 | addr_counter ZW ch0=(0,0) ch1=(0,0) mask=0xf old_trisc0_78->old_trisc0_79 old_trisc0_80 080  trisc0  00006238  lw add1.TENSIX_PC_UNPACK_SYNC a5 <- add1.TENSIX_PC_UNPACK_SYNC (PC_BUF_SEM[5]) old_trisc0_79->old_trisc0_80 old_trisc0_80->old_trisc0_81 old_trisc0_82 082  trisc0  0000624c  sw tensix_cfg+0x4b0 t3=unknown old_trisc0_81->old_trisc0_82 old_trisc0_83 083  trisc0  00006250  sw add1.TENSIX_PC_UNPACK_SYNC zero=0x00000000 old_trisc0_82->old_trisc0_83 old_trisc0_84 084  trisc0  00006254  tensix Tensix instruction ttstallwait 8,1024 old_trisc0_83->old_trisc0_84 old_trisc0_95 095  trisc0  000062bc  sw add1.TENSIX_PC_UNPACK_SYNC zero=0x00000000 old_trisc0_83->old_trisc0_95 pcbuf:0x34 old_trisc0_85 085  trisc0  00006258  tensix Tensix instruction ttmop 1,0,0 old_trisc0_84->old_trisc0_85 old_trisc0_86 086  trisc0  0000625c  tensix Tensix instruction ttsemget 32 old_trisc0_85->old_trisc0_86 old_trisc0_86->old_trisc0_87 old_trisc0_98 098  trisc0  000062c8  tensix Tensix instruction ttsemget 32 old_trisc0_86->old_trisc0_98 tensix_sem:32 old_trisc0_88 088  trisc0  00006264  tensix Tensix instruction ttsetc16 41,257 | thread_cfg[41] := 0x101 (UNPACK_MISC_CFG) old_trisc0_87->old_trisc0_88 old_trisc0_99 099  trisc0  000062d0  sw add1.TRISC0_UNP_CFG_CONTEXT t3=unknown old_trisc0_87->old_trisc0_99 old_trisc0_89 089  trisc0  00006278  sh TriscCB[0].tiles_acked_received a4=unknown old_trisc0_88->old_trisc0_89 old_trisc0_89->old_trisc0_90 old_trisc1_6 006  trisc1  000062d8  sw TriscCB[0].tiles_acked_received zero=0x00000000 old_trisc0_89->old_trisc1_6 old_trisc0_91 091  trisc0  00006280  tensix Tensix instruction ttstallwait 32,6 old_trisc0_90->old_trisc0_91 old_trisc0_92 092  trisc0  00006284  tensix Tensix instruction t5=TTSTOREREG(4, 0x12008) old_trisc0_90->old_trisc0_92 tensix_instr old_trisc0_91->old_trisc0_92 old_trisc0_93 093  trisc0  00006294  sw TriscCB[0].rd_ptr a1=unknown old_trisc0_92->old_trisc0_93 old_trisc1_17 017  trisc1  00006394  tensix Tensix instruction a4=TTZEROACC(3, 0, 0, 1) old_trisc0_92->old_trisc1_17 tensix_instr old_trisc0_94 094  trisc0  000062b8  sw tensix_cfg+0x4b4 t3=unknown old_trisc0_93->old_trisc0_94 old_trisc1_5 005  trisc1  000062cc  sw TriscCB[0].rd_ptr zero=0x00000000 old_trisc0_93->old_trisc1_5 old_trisc0_94->old_trisc0_95 old_trisc0_95->old_trisc0_96 old_trisc0_97 097  trisc0  000062c4  tensix Tensix instruction ttmop 1,0,0 old_trisc0_96->old_trisc0_97 old_trisc0_97->old_trisc0_98 old_trisc0_98->old_trisc0_99 old_trisc0_100 100  trisc0  000062d8  tensix Tensix instruction ttsetc16 41,0 | thread_cfg[41] := 0x0 (UNPACK_MISC_CFG) old_trisc0_99->old_trisc0_100 old_trisc0_99->old_trisc2_0 old_trisc1_1 001  trisc1  000062ac  sw TriscCB[0].page_size zero=0x00000000 old_trisc1_0->old_trisc1_1 old_trisc1_10 010  trisc1  00006340  sw TriscCB[0].num_pages a1=unknown old_trisc1_0->old_trisc1_10 old_trisc1_2 002  trisc1  000062b0  sw TriscCB[0].fifo_limit zero=0x00000000 old_trisc1_1->old_trisc1_2 old_trisc1_9 009  trisc1  0000632c  sw TriscCB[0].page_size a2=unknown old_trisc1_1->old_trisc1_9 old_trisc1_3 003  trisc1  000062b4  sw add1.TRISC1_UNPACK_TILE_NUM_FACES zero=0x00000000 old_trisc1_2->old_trisc1_3 old_trisc1_8 008  trisc1  00006328  sw TriscCB[0].fifo_limit a1=unknown old_trisc1_2->old_trisc1_8 old_trisc1_4 004  trisc1  000062c8  sw TriscCB[0].wr_ptr zero=0x00000000 old_trisc1_3->old_trisc1_4 old_trisc1_7 007  trisc1  00006324  sw add1.TRISC1_UNPACK_TILE_NUM_FACES a0=unknown old_trisc1_3->old_trisc1_7 old_trisc1_4->old_trisc1_5 old_trisc1_5->old_trisc1_6 old_trisc1_11 011  trisc1  0000634c  sw TriscCB[0].rd_ptr a4=unknown old_trisc1_5->old_trisc1_11 old_trisc1_6->old_trisc1_7 old_ncrisc_6 006  ncrisc  000059f8  lw NM.RTA_L1_BASE_PTR a5 <- NM.RTA_L1_BASE_PTR old_trisc1_6->old_ncrisc_6 old_trisc1_7->old_trisc1_8 old_trisc1_8->old_trisc1_9 old_trisc1_9->old_trisc1_10 old_trisc1_10->old_trisc1_11 old_trisc1_12 012  trisc1  00006350  lw TensixL1.GO_MSG_INDEX a4 <- TensixL1.GO_MSG_INDEX old_trisc1_11->old_trisc1_12 old_trisc1_13 013  trisc1  00006374  tensix Tensix instruction ttsetc16 13,0 | thread_cfg[13] := 0x0 (ADDR_MOD_AB_SEC1) old_trisc1_12->old_trisc1_13 old_trisc1_14 014  trisc1  00006378  tensix Tensix instruction ttsetc16 29,0 | thread_cfg[29] := 0x0 (ADDR_MOD_DST_SEC1) old_trisc1_13->old_trisc1_14 old_trisc1_15 015  trisc1  0000637c  tensix Tensix instruction ttsetc16 48,0 | thread_cfg[48] := 0x0 (ADDR_MOD_BIAS_SEC1) old_trisc1_14->old_trisc1_15 old_trisc1_16 016  trisc1  00006388  lw TM.DATA1['rta_l1_base'] a5 <- TM.DATA1['rta_l1_base'] old_trisc1_15->old_trisc1_16 old_trisc1_16->old_trisc1_17 old_trisc1_18 018  trisc1  0000639c  tensix Tensix instruction ttsetc16 15,0 | thread_cfg[15] := 0x0 (ADDR_MOD_AB_SEC3) old_trisc1_17->old_trisc1_18 old_trisc1_44 044  trisc1  0000644c  tensix Tensix instruction a0=TTSETC16(1) old_trisc1_17->old_trisc1_44 tensix_instr old_trisc1_19 019  trisc1  000063a0  tensix Tensix instruction ttsetc16 31,0 | thread_cfg[31] := 0x0 (ADDR_MOD_DST_SEC3) old_trisc1_18->old_trisc1_19 old_trisc1_20 020  trisc1  000063a4  tensix Tensix instruction ttsetc16 50,0 | thread_cfg[50] := 0x0 (ADDR_MOD_BIAS_SEC3) old_trisc1_19->old_trisc1_20 old_trisc1_21 021  trisc1  000063a8  tensix Tensix instruction ttsetc16 12,1 | thread_cfg[12] := 0x1 (ADDR_MOD_AB_SEC0) old_trisc1_20->old_trisc1_21 old_trisc1_22 022  trisc1  000063ac  tensix Tensix instruction ttsetc16 28,1 | thread_cfg[28] := 0x1 (ADDR_MOD_DST_SEC0) old_trisc1_21->old_trisc1_22 old_trisc1_23 023  trisc1  000063b0  tensix Tensix instruction ttsetc16 47,0 | thread_cfg[47] := 0x0 (ADDR_MOD_BIAS_SEC0) old_trisc1_22->old_trisc1_23 old_trisc1_24 024  trisc1  000063b4  tensix Tensix instruction ttsetc16 14,8 | thread_cfg[14] := 0x8 (ADDR_MOD_AB_SEC2) old_trisc1_23->old_trisc1_24 old_trisc1_25 025  trisc1  000063b8  tensix Tensix instruction ttsetc16 30,8 | thread_cfg[30] := 0x8 (ADDR_MOD_DST_SEC2) old_trisc1_24->old_trisc1_25 old_trisc1_26 026  trisc1  000063bc  tensix Tensix instruction ttsetc16 49,0 | thread_cfg[49] := 0x0 (ADDR_MOD_BIAS_SEC2) old_trisc1_25->old_trisc1_26 old_trisc1_26->old_trisc1_27 old_trisc1_28 028  trisc1  000063d0  lw add1.TENSIX_PC_BUF_MOP_SYNC a0 <- add1.TENSIX_PC_BUF_MOP_SYNC (PC_BUF_MOP_SYNC) old_trisc1_27->old_trisc1_28 old_trisc1_27->old_trisc1_28 pcbuf:0x8 old_trisc1_58 058  trisc1  000064a0  sw add1.TENSIX_PC_BUF_MOP_SYNC a2=unknown old_trisc1_27->old_trisc1_58 pcbuf:0x8 old_trisc1_28->old_trisc1_29 old_trisc1_29->old_trisc1_30 old_trisc1_60 060  trisc1  000064b8  sw add1.TENSIX_MOP_CFG a7=0x00000004 old_trisc1_29->old_trisc1_60 mop:0 old_trisc1_30->old_trisc1_31 old_trisc1_61 061  trisc1  000064bc  sw tensix_mop_cfg+0x4 a4=0x00000002 old_trisc1_30->old_trisc1_61 mop:1 old_trisc1_31->old_trisc1_32 old_trisc1_62 062  trisc1  000064c4  sw tensix_mop_cfg+0x8 a2=0x02000000 old_trisc1_31->old_trisc1_62 mop:2 old_trisc1_32->old_trisc1_33 old_trisc1_63 063  trisc1  000064cc  sw tensix_mop_cfg+0xc a4=0x37c00003 old_trisc1_32->old_trisc1_63 mop:3 old_trisc1_64 064  trisc1  000064d0  sw tensix_mop_cfg+0x10 a2=0x02000000 old_trisc1_33->old_trisc1_34 old_trisc1_33->old_trisc1_64 mop:4 old_trisc1_34->old_trisc1_35 old_trisc1_65 065  trisc1  000064d8  sw tensix_mop_cfg+0x14 a4=0x1200a000 old_trisc1_34->old_trisc1_65 mop:5 old_trisc1_35->old_trisc1_36 old_trisc1_66 066  trisc1  000064dc  sw tensix_mop_cfg+0x18 a2=0x02000000 old_trisc1_35->old_trisc1_66 mop:6 old_trisc1_36->old_trisc1_37 old_trisc1_67 067  trisc1  000064e0  sw tensix_mop_cfg+0x1c a4=0x1200a000 old_trisc1_36->old_trisc1_67 mop:7 old_trisc1_38 038  trisc1  00006418  tensix Tensix instruction ttsetc16 7,0 | thread_cfg[7] := 0x0 (CLR_DVALID) old_trisc1_37->old_trisc1_38 old_trisc1_68 068  trisc1  000064e4  sw tensix_mop_cfg+0x20 a4=0x1200a000 old_trisc1_37->old_trisc1_68 mop:8 old_trisc1_39 039  trisc1  0000641c  tensix Tensix instruction ttsetrwc 0,0,0,0,0,15 old_trisc1_38->old_trisc1_39 old_trisc1_40 040  trisc1  00006428  sw add1.TENSIX_PC_BUF_SYNC a5=unknown old_trisc1_39->old_trisc1_40 old_trisc1_41 041  trisc1  0000642c  lw add1.TENSIX_PC_BUF_SYNC a5 <- add1.TENSIX_PC_BUF_SYNC (PC_BUF_SYNC) old_trisc1_40->old_trisc1_41 old_trisc1_40->old_trisc1_41 pcbuf:0x4 old_trisc2_62 062  trisc2  00006d28  sw add1.TENSIX_PC_BUF_SYNC a5=unknown old_trisc1_40->old_trisc2_62 pcbuf:0x4 old_trisc1_42 042  trisc1  00006434  lw tensix_pc_buf+0x24 a5 <- tensix_pc_buf+0x24 (PC_BUF_SEM[1]) old_trisc1_41->old_trisc1_42 old_trisc1_43 043  trisc1  00006440  tensix Tensix instruction ttseminit 2,0,2 old_trisc1_42->old_trisc1_43 old_trisc1_43->old_trisc1_44 old_trisc1_45 045  trisc1  00006454  tensix Tensix instruction a5=TTRMWCIB0(8, 8, 0xDC) old_trisc1_44->old_trisc1_45 old_trisc1_44->old_trisc1_45 tensix_instr old_trisc1_46 046  trisc1  0000645c  sw TM.DATA1['dest_offset_id'] zero=0x00000000 old_trisc1_45->old_trisc1_46 old_trisc1_48 048  trisc1  0000646c  tensix Tensix instruction a5=TTRMWCIB3(0x80, 0, 1) old_trisc1_45->old_trisc1_48 tensix_instr old_trisc1_47 047  trisc1  00006460  tensix Tensix instruction ttstallwait 128,16 old_trisc1_46->old_trisc1_47 old_trisc1_78 078  trisc1  00006510  lw TM.DATA1['dest_offset_id'] a4 <- TM.DATA1['dest_offset_id'] old_trisc1_46->old_trisc1_78 old_trisc1_103 103  trisc1  00006594  lw TM.DATA1['dest_offset_id'] a5 <- TM.DATA1['dest_offset_id'] old_trisc1_46->old_trisc1_103 old_trisc1_104 104  trisc1  0000659c  sw TM.DATA1['dest_offset_id'] a4=unknown old_trisc1_46->old_trisc1_104 old_trisc1_47->old_trisc1_48 old_trisc1_49 049  trisc1  00006470  tensix Tensix instruction ttsetc16 15,0 | thread_cfg[15] := 0x0 (ADDR_MOD_AB_SEC3) old_trisc1_48->old_trisc1_49 old_trisc1_80 080  trisc1  0000652c  tensix Tensix instruction a4=unknown old_trisc1_48->old_trisc1_80 tensix_instr old_trisc1_50 050  trisc1  00006474  tensix Tensix instruction ttsetc16 31,0 | thread_cfg[31] := 0x0 (ADDR_MOD_DST_SEC3) old_trisc1_49->old_trisc1_50 old_trisc1_51 051  trisc1  00006478  tensix Tensix instruction ttsetc16 50,0 | thread_cfg[50] := 0x0 (ADDR_MOD_BIAS_SEC3) old_trisc1_50->old_trisc1_51 old_trisc1_52 052  trisc1  0000647c  tensix Tensix instruction ttsetc16 12,1 | thread_cfg[12] := 0x1 (ADDR_MOD_AB_SEC0) old_trisc1_51->old_trisc1_52 old_trisc1_53 053  trisc1  00006480  tensix Tensix instruction ttsetc16 28,1 | thread_cfg[28] := 0x1 (ADDR_MOD_DST_SEC0) old_trisc1_52->old_trisc1_53 old_trisc1_54 054  trisc1  00006484  tensix Tensix instruction ttsetc16 47,0 | thread_cfg[47] := 0x0 (ADDR_MOD_BIAS_SEC0) old_trisc1_53->old_trisc1_54 old_trisc1_55 055  trisc1  00006488  tensix Tensix instruction ttsetc16 14,8 | thread_cfg[14] := 0x8 (ADDR_MOD_AB_SEC2) old_trisc1_54->old_trisc1_55 old_trisc1_56 056  trisc1  0000648c  tensix Tensix instruction ttsetc16 30,8 | thread_cfg[30] := 0x8 (ADDR_MOD_DST_SEC2) old_trisc1_55->old_trisc1_56 old_trisc1_57 057  trisc1  00006490  tensix Tensix instruction ttsetc16 49,0 | thread_cfg[49] := 0x0 (ADDR_MOD_BIAS_SEC2) old_trisc1_56->old_trisc1_57 old_trisc1_57->old_trisc1_58 old_trisc1_59 059  trisc1  000064a4  lw add1.TENSIX_PC_BUF_MOP_SYNC t1 <- add1.TENSIX_PC_BUF_MOP_SYNC (PC_BUF_MOP_SYNC) old_trisc1_58->old_trisc1_59 old_trisc1_58->old_trisc1_59 pcbuf:0x8 old_trisc2_41 041  trisc2  00006ca8  sw add1.TENSIX_PC_BUF_MOP_SYNC a5=unknown old_trisc1_58->old_trisc2_41 pcbuf:0x8 old_trisc1_59->old_trisc1_60 old_trisc1_60->old_trisc1_61 old_trisc2_43 043  trisc2  00006cc0  sw add1.TENSIX_MOP_CFG t3=0x00000004 old_trisc1_60->old_trisc2_43 mop:0 old_trisc1_61->old_trisc1_62 old_trisc2_44 044  trisc2  00006cc4  sw tensix_mop_cfg+0x4 t3=0x00000004 old_trisc1_61->old_trisc2_44 mop:1 old_trisc1_62->old_trisc1_63 old_trisc2_45 045  trisc2  00006cc8  sw tensix_mop_cfg+0x8 t1=0x02000000 old_trisc1_62->old_trisc2_45 mop:2 old_trisc1_63->old_trisc1_64 old_trisc2_46 046  trisc2  00006ccc  sw tensix_mop_cfg+0xc t1=0x02000000 old_trisc1_63->old_trisc2_46 mop:3 old_trisc1_64->old_trisc1_65 old_trisc1_96 096  trisc1  00006570  tensix Tensix instruction ttreplay 0,5,0,0 old_trisc2_47 047  trisc2  00006cd0  sw tensix_mop_cfg+0x10 t1=0x02000000 old_trisc1_64->old_trisc2_47 mop:4 old_trisc1_65->old_trisc1_66 old_trisc2_48 048  trisc2  00006cd8  sw tensix_mop_cfg+0x14 t3=0x41000000 old_trisc1_65->old_trisc2_48 mop:5 old_trisc1_66->old_trisc1_67 old_trisc2_49 049  trisc2  00006ce0  sw tensix_mop_cfg+0x18 t1=0x02000000 old_trisc1_66->old_trisc2_49 mop:6 old_trisc1_67->old_trisc1_68 old_trisc2_50 050  trisc2  00006ce8  sw tensix_mop_cfg+0x1c t1=0x41008001 old_trisc1_67->old_trisc2_50 mop:7 old_trisc1_69 069  trisc1  000064e8  tensix Tensix instruction ttsetc16 7,0 | thread_cfg[7] := 0x0 (CLR_DVALID) old_trisc1_68->old_trisc1_69 old_trisc2_51 051  trisc2  00006cf0  sw tensix_mop_cfg+0x20 t1=0x41010000 old_trisc1_68->old_trisc2_51 mop:8 old_trisc1_70 070  trisc1  000064ec  tensix Tensix instruction ttsetrwc 0,0,0,0,0,15 old_trisc1_69->old_trisc1_70 old_trisc1_71 071  trisc1  000064f0  tensix Tensix instruction sfploadi L0,0,10 old_trisc1_70->old_trisc1_71 old_trisc1_72 072  trisc1  000064f4  tensix Tensix instruction sfploadi L0,0,8 old_trisc1_71->old_trisc1_72 old_trisc1_73 073  trisc1  000064f8  tensix Tensix instruction sfpconfig 15,0,0 old_trisc1_72->old_trisc1_73 old_trisc1_74 074  trisc1  000064fc  tensix Tensix instruction ttsetc16 19,0 | thread_cfg[19] := 0x0 (ADDR_MOD_AB_SEC7) old_trisc1_73->old_trisc1_74 old_trisc1_75 075  trisc1  00006500  tensix Tensix instruction ttsetc16 35,0 | thread_cfg[35] := 0x0 (ADDR_MOD_DST_SEC7) old_trisc1_74->old_trisc1_75 old_trisc1_76 076  trisc1  00006504  tensix Tensix instruction ttsetc16 54,0 | thread_cfg[54] := 0x0 (ADDR_MOD_BIAS_SEC7) old_trisc1_75->old_trisc1_76 old_trisc1_77 077  trisc1  00006508  tensix Tensix instruction ttsetrwc 0,0,0,0,0,15 old_trisc1_76->old_trisc1_77 old_trisc1_77->old_trisc1_78 old_trisc1_79 079  trisc1  0000651c  tensix Tensix instruction ttsemwait 322,2,2 old_trisc1_78->old_trisc1_79 old_trisc1_79->old_trisc1_80 old_trisc1_81 081  trisc1  00006530  tensix Tensix instruction ttmop 1,0,0 old_trisc1_80->old_trisc1_81 old_trisc1_83 083  trisc1  00006538  tensix Tensix instruction a4=unknown old_trisc1_80->old_trisc1_83 tensix_instr old_trisc1_82 082  trisc1  00006534  tensix Tensix instruction ttsetrwc 0,0,0,0,0,4 old_trisc1_81->old_trisc1_82 old_trisc1_82->old_trisc1_83 old_trisc1_84 084  trisc1  0000653c  tensix Tensix instruction ttstallwait 256,16 old_trisc1_83->old_trisc1_84 old_trisc1_106 106  trisc1  000065b4  tensix Tensix instruction a5=unknown old_trisc1_83->old_trisc1_106 tensix_instr old_trisc1_85 085  trisc1  00006544  tensix Tensix instruction ttreplay 0,5,1,1 old_trisc1_84->old_trisc1_85 old_trisc1_86 086  trisc1  00006548  tensix Tensix instruction sfpload L0,0,0,7 old_trisc1_85->old_trisc1_86 old_trisc1_87 087  trisc1  0000654c  tensix Tensix instruction sfpaddi L0,16256,0 old_trisc1_86->old_trisc1_87 old_trisc1_88 088  trisc1  00006550  tensix Tensix instruction sfpnop old_trisc1_87->old_trisc1_88 old_trisc1_89 089  trisc1  00006554  tensix Tensix instruction sfpstore 0,L0,0,7 old_trisc1_88->old_trisc1_89 old_trisc1_90 090  trisc1  00006558  tensix Tensix instruction ttincrwc 0,2,0,0 old_trisc1_89->old_trisc1_90 old_trisc1_91 091  trisc1  0000655c  tensix Tensix instruction ttreplay 0,5,0,0 old_trisc1_90->old_trisc1_91 old_trisc1_92 092  trisc1  00006560  tensix Tensix instruction ttreplay 0,5,0,0 old_trisc1_91->old_trisc1_92 old_trisc1_93 093  trisc1  00006564  tensix Tensix instruction ttreplay 0,5,0,0 old_trisc1_92->old_trisc1_93 old_trisc1_94 094  trisc1  00006568  tensix Tensix instruction ttreplay 0,5,0,0 old_trisc1_93->old_trisc1_94 old_trisc1_95 095  trisc1  0000656c  tensix Tensix instruction ttreplay 0,5,0,0 old_trisc1_94->old_trisc1_95 old_trisc1_95->old_trisc1_96 old_trisc1_97 097  trisc1  00006574  tensix Tensix instruction ttreplay 0,5,0,0 old_trisc1_96->old_trisc1_97 old_trisc1_98 098  trisc1  00006578  tensix Tensix instruction ttsetrwc 0,4,8,0,0,4 old_trisc1_97->old_trisc1_98 old_trisc1_99 099  trisc1  0000657c  tensix Tensix instruction ttsetrwc 0,4,8,0,0,4 old_trisc1_98->old_trisc1_99 old_trisc1_100 100  trisc1  00006588  tensix Tensix instruction ttsetrwc 0,0,0,0,0,4 old_trisc1_99->old_trisc1_100 old_trisc1_101 101  trisc1  0000658c  tensix Tensix instruction ttstallwait 2,2064 old_trisc1_100->old_trisc1_101 old_trisc1_102 102  trisc1  00006590  tensix Tensix instruction ttsempost 2 old_trisc1_101->old_trisc1_102 old_trisc1_102->old_trisc1_103 old_trisc2_79 079  trisc2  00006df4  tensix Tensix instruction ttsemwait 1,2,1 old_trisc1_102->old_trisc2_79 tensix_sem:2 old_trisc2_97 097  trisc2  00006e98  tensix Tensix instruction ttsemget 2 old_trisc1_102->old_trisc2_97 tensix_sem:2 old_trisc1_103->old_trisc1_104 old_trisc1_105 105  trisc1  000065a0  tensix Tensix instruction ttstallwait 128,2064 old_trisc1_104->old_trisc1_105 old_trisc2_64 064  trisc2  00006d30  sw TM.DATA1['dest_offset_id'] zero=0x00000000 old_trisc1_104->old_trisc2_64 old_trisc1_105->old_trisc1_106 old_trisc1_107 107  trisc1  000065ec  tensix Tensix instruction a3=TTSFPLOAD(0xE, 0xE) old_trisc1_106->old_trisc1_107 old_trisc1_106->old_trisc1_107 tensix_instr old_trisc1_108 108  trisc1  000065f8  tensix Tensix instruction a0=TTSFPLOADI(0, 8) old_trisc1_107->old_trisc1_108 old_trisc1_107->old_trisc1_108 tensix_instr old_trisc1_109 109  trisc1  000065fc  tensix Tensix instruction ttreplay 0,5,1,1 old_trisc1_108->old_trisc1_109 old_trisc2_6 006  trisc2  00006bac  tensix Tensix instruction t5=TTSETDMAREG(0, 0, 0, 0x38) old_trisc1_108->old_trisc2_6 tensix_instr old_trisc1_110 110  trisc1  00006600  tensix Tensix instruction sfpload L1,0,0,7 old_trisc1_109->old_trisc1_110 old_trisc1_111 111  trisc1  00006604  tensix Tensix instruction sfpadd L1,L10,L1,L0,0 old_trisc1_110->old_trisc1_111 old_trisc1_112 112  trisc1  00006608  tensix Tensix instruction sfpnop old_trisc1_111->old_trisc1_112 old_trisc1_113 113  trisc1  0000660c  tensix Tensix instruction sfpstore 0,L1,0,7 old_trisc1_112->old_trisc1_113 old_trisc1_114 114  trisc1  00006610  tensix Tensix instruction ttincrwc 0,2,0,0 old_trisc1_113->old_trisc1_114 old_trisc1_115 115  trisc1  00006614  tensix Tensix instruction ttreplay 0,5,0,0 old_trisc1_114->old_trisc1_115 old_trisc1_116 116  trisc1  00006618  tensix Tensix instruction ttreplay 0,5,0,0 old_trisc1_115->old_trisc1_116 old_trisc1_117 117  trisc1  0000661c  tensix Tensix instruction ttreplay 0,5,0,0 old_trisc1_116->old_trisc1_117 old_trisc1_118 118  trisc1  00006620  tensix Tensix instruction ttreplay 0,5,0,0 old_trisc1_117->old_trisc1_118 old_trisc1_119 119  trisc1  00006624  tensix Tensix instruction ttreplay 0,5,0,0 old_trisc1_118->old_trisc1_119 old_trisc1_120 120  trisc1  00006628  tensix Tensix instruction ttreplay 0,5,0,0 old_trisc1_119->old_trisc1_120 old_trisc1_121 121  trisc1  0000662c  tensix Tensix instruction sfpload L1,0,0,7 old_trisc1_120->old_trisc1_121 old_trisc1_122 122  trisc1  00006630  tensix Tensix instruction sfpadd L0,L10,L1,L0,0 old_trisc1_121->old_trisc1_122 old_trisc1_123 123  trisc1  00006634  tensix Tensix instruction sfpnop old_trisc1_122->old_trisc1_123 old_trisc1_124 124  trisc1  00006638  tensix Tensix instruction sfpstore 0,L0,0,7 old_trisc1_123->old_trisc1_124 old_trisc1_125 125  trisc1  0000663c  tensix Tensix instruction ttincrwc 0,2,0,0 old_trisc1_124->old_trisc1_125 old_trisc2_1 001  trisc2  00006b1c  sw add1.TRISC0_UNP_CFG_CONTEXT a0=unknown old_trisc2_0->old_trisc2_1 old_trisc2_32 032  trisc2  00006c68  sw tensix_regfile+0x40 t3=unknown old_trisc2_2 002  trisc2  00006b48  lw TensixL1.GO_MSG_INDEX a4 <- TensixL1.GO_MSG_INDEX old_trisc2_1->old_trisc2_2 old_trisc2_3 003  trisc2  00006b74  lw TM.DATA1['my_logical_y'] a5 <- TM.DATA1['my_logical_y'] old_trisc2_2->old_trisc2_3 old_trisc2_4 004  trisc2  00006b7c  lw TM.LOCAL_END[1] a4 <- TM.LOCAL_END[1] old_trisc2_3->old_trisc2_4 old_trisc2_5 005  trisc2  00006b88  lw TriscCB[16].page_size t3 <- TriscCB[16].page_size old_trisc2_4->old_trisc2_5 old_trisc2_5->old_trisc2_6 old_trisc2_7 007  trisc2  00006bb8  tensix Tensix instruction a6=TTSETDMAREG(0, 0x20, 0, 0x39) old_trisc2_6->old_trisc2_7 old_trisc2_6->old_trisc2_7 tensix_instr old_trisc2_8 008  trisc2  00006bc4  tensix Tensix instruction t4=TTSETDMAREG(0, 0x200, 0, 0x3A) old_trisc2_7->old_trisc2_8 old_trisc2_7->old_trisc2_8 tensix_instr old_trisc2_9 009  trisc2  00006bcc  tensix Tensix instruction a0=TTSETDMAREG(0, 0x800, 0, 0x3B) old_trisc2_8->old_trisc2_9 old_trisc2_8->old_trisc2_9 tensix_instr old_trisc2_10 010  trisc2  00006bd0  tensix Tensix instruction ttstallwait 128,1 old_trisc2_9->old_trisc2_10 old_trisc2_16 016  trisc2  00006bf0  tensix Tensix instruction a4=TTRMWCIB3(0x1E, 0xA, 1) old_trisc2_9->old_trisc2_16 tensix_instr old_trisc2_11 011  trisc2  00006bd4  tensix Tensix instruction ttwrcfg 28,0,12 | cfg[12] := dma_reg[28] 32b (PCK0_ADDR_CTRL_XY_REG_0) old_trisc2_10->old_trisc2_11 old_trisc2_12 012  trisc2  00006bd8  tensix Tensix instruction ttwrcfg 29,0,13 | cfg[13] := dma_reg[29] 32b (PCK0_ADDR_CTRL_ZW_REG_0) old_trisc2_11->old_trisc2_12 old_trisc2_13 013  trisc2  00006bdc  tensix Tensix instruction ttnop old_trisc2_12->old_trisc2_13 old_trisc2_14 014  trisc2  00006be0  tensix Tensix instruction ttnop old_trisc2_13->old_trisc2_14 old_trisc2_15 015  trisc2  00006be4  tensix Tensix instruction ttatgetm 0 old_trisc2_14->old_trisc2_15 old_trisc2_15->old_trisc2_16 old_trisc2_17 017  trisc2  00006bfc  tensix Tensix instruction a4=TTRMWCIB0(0xFC, 0, 2) old_trisc2_16->old_trisc2_17 old_trisc2_16->old_trisc2_17 tensix_instr old_trisc2_18 018  trisc2  00006c08  tensix Tensix instruction a4=TTRMWCIB1(0xFF, 0, 2) old_trisc2_17->old_trisc2_18 old_trisc2_17->old_trisc2_18 tensix_instr old_trisc2_19 019  trisc2  00006c14  tensix Tensix instruction a4=TTRMWCIB2(0x3F, 0, 2) old_trisc2_18->old_trisc2_19 old_trisc2_18->old_trisc2_19 tensix_instr old_trisc2_20 020  trisc2  00006c18  tensix Tensix instruction ttatrelm 0 old_trisc2_19->old_trisc2_20 old_trisc2_37 037  trisc2  00006c8c  tensix Tensix instruction a1=TTSETADCXX(4, 0xF) old_trisc2_19->old_trisc2_37 tensix_instr old_trisc2_21 021  trisc2  00006c20  sw tensix_cfg+0x490 a1=0x00040000 | bank1.cfg[68] value: THCON_SEC0_REG1_Row_start_section_size=0, THCON_SEC0_REG1_Exp_section_size=4 old_trisc2_20->old_trisc2_21 old_trisc2_22 022  trisc2  00006c28  sw tensix_cfg+0x498 a4=0x00000551 | bank1.cfg[70] value: THCON_SEC0_REG1_Disable_zero_compress=1, THCON_SEC0_REG1_Add_l1_dest_addr_offset=0,... old_trisc2_21->old_trisc2_22 old_trisc2_23 023  trisc2  00006c2c  sw tensix_cfg+0x3c8 zero=0x00000000 | bank1.cfg[18] value: PCK_DEST_RD_CTRL_Read_32b_data=0, PCK_DEST_RD_CTRL_Read_unsigned=0,... old_trisc2_22->old_trisc2_23 old_trisc2_24 024  trisc2  00006c34  sw tensix_regfile+0xd0 a1=0x00040000 | dma_reg[52] value: lo16=0x0000, hi16=0x0004 old_trisc2_23->old_trisc2_24 old_trisc2_25 025  trisc2  00006c3c  lw tensix_regfile+0xd0 t0 <- tensix_regfile+0xd0 (dma_reg[52]) old_trisc2_24->old_trisc2_25 old_trisc2_24->old_trisc2_25 dma_reg:52 old_trisc2_26 026  trisc2  00006c50  sw tensix_cfg+0x3f0 a1=0x00001000 | bank1.cfg[28] value: PACK_COUNTERS_SEC0_pack_per_xy_plane=0, PACK_COUNTERS_SEC0_pack_reads_per_xy_plane=16,... old_trisc2_25->old_trisc2_26 old_trisc2_27 027  trisc2  00006c54  sw tensix_cfg+0x3f4 a1=0x00001000 | bank1.cfg[29] value: PACK_COUNTERS_SEC1_pack_per_xy_plane=0, PACK_COUNTERS_SEC1_pack_reads_per_xy_plane=16,... old_trisc2_26->old_trisc2_27 old_trisc2_28 028  trisc2  00006c58  sw tensix_cfg+0x3f8 a1=0x00001000 | bank1.cfg[30] value: PACK_COUNTERS_SEC2_pack_per_xy_plane=0, PACK_COUNTERS_SEC2_pack_reads_per_xy_plane=16,... old_trisc2_27->old_trisc2_28 old_trisc2_29 029  trisc2  00006c5c  sw tensix_cfg+0x3fc a1=0x00001000 | bank1.cfg[31] value: PACK_COUNTERS_SEC3_pack_per_xy_plane=0, PACK_COUNTERS_SEC3_pack_reads_per_xy_plane=16,... old_trisc2_28->old_trisc2_29 old_trisc2_30 030  trisc2  00006c60  sw tensix_cfg+0x3e0 t1=0x0000ffff | bank1.cfg[24] value: PCK_EDGE_OFFSET_SEC0_mask=65535, PCK_EDGE_MODE_mode=0, PCK_EDGE_TILE_ROW_SET_SELECT_select=0 old_trisc2_29->old_trisc2_30 old_trisc2_31 031  trisc2  00006c64  sw tensix_cfg+0x3d0 zero=0x00000000 | bank1.cfg[20] value: TILE_ROW_SET_MAPPING_0_row_set_mapping_0=0, TILE_ROW_SET_MAPPING_0_row_set_mapping_1=0,... old_trisc2_30->old_trisc2_31 old_trisc2_31->old_trisc2_32 old_trisc2_33 033  trisc2  00006c6c  sw tensix_regfile+0x44 zero=0x00000000 | dma_reg[17] value: lo16=0x0000, hi16=0x0000 old_trisc2_32->old_trisc2_33 old_trisc2_34 034  trisc2  00006c70  sw tensix_regfile+0x48 zero=0x00000000 | dma_reg[18] value: lo16=0x0000, hi16=0x0000 old_trisc2_33->old_trisc2_34 old_trisc2_35 035  trisc2  00006c74  sw tensix_regfile+0x4c zero=0x00000000 | dma_reg[19] value: lo16=0x0000, hi16=0x0000 old_trisc2_34->old_trisc2_35 old_trisc2_36 036  trisc2  00006c7c  lw tensix_regfile+0x4c a5 <- tensix_regfile+0x4c (dma_reg[19]) old_trisc2_35->old_trisc2_36 old_trisc2_35->old_trisc2_36 dma_reg:19 old_trisc2_36->old_trisc2_37 old_trisc2_38 038  trisc2  00006c90  tensix Tensix instruction ttsetc16 37,260 | thread_cfg[37] := 0x104 (ADDR_MOD_PACK_SEC0) old_trisc2_37->old_trisc2_38 old_trisc2_52 052  trisc2  00006cf4  tensix Tensix instruction t5=TTSETDMAREG(0, 0, 0, 0x38) old_trisc2_37->old_trisc2_52 tensix_instr old_trisc2_39 039  trisc2  00006c94  tensix Tensix instruction ttsetc16 38,10272 | thread_cfg[38] := 0x2820 (ADDR_MOD_PACK_SEC1) old_trisc2_38->old_trisc2_39 old_trisc2_40 040  trisc2  00006c98  tensix Tensix instruction ttsetc16 39,4384 | thread_cfg[39] := 0x1120 (ADDR_MOD_PACK_SEC2) old_trisc2_39->old_trisc2_40 old_trisc2_40->old_trisc2_41 old_trisc2_42 042  trisc2  00006cac  lw add1.TENSIX_PC_BUF_MOP_SYNC t0 <- add1.TENSIX_PC_BUF_MOP_SYNC (PC_BUF_MOP_SYNC) old_trisc2_41->old_trisc2_42 old_trisc2_41->old_trisc2_42 pcbuf:0x8 old_trisc2_42->old_trisc2_43 old_trisc2_43->old_trisc2_44 old_trisc2_44->old_trisc2_45 old_trisc2_45->old_trisc2_46 old_trisc2_46->old_trisc2_47 old_trisc2_47->old_trisc2_48 old_trisc2_48->old_trisc2_49 old_trisc2_49->old_trisc2_50 old_trisc2_50->old_trisc2_51 old_trisc2_51->old_trisc2_52 old_trisc2_53 053  trisc2  00006cf8  tensix Tensix instruction a6=TTSETDMAREG(0, 0x20, 0, 0x39) old_trisc2_52->old_trisc2_53 old_trisc2_52->old_trisc2_53 tensix_instr old_trisc2_54 054  trisc2  00006cfc  tensix Tensix instruction t4=TTSETDMAREG(0, 0x200, 0, 0x3A) old_trisc2_53->old_trisc2_54 old_trisc2_53->old_trisc2_54 tensix_instr old_trisc2_55 055  trisc2  00006d00  tensix Tensix instruction a0=TTSETDMAREG(0, 0x800, 0, 0x3B) old_trisc2_54->old_trisc2_55 old_trisc2_54->old_trisc2_55 tensix_instr old_trisc2_56 056  trisc2  00006d04  tensix Tensix instruction ttstallwait 128,1 old_trisc2_55->old_trisc2_56 old_trisc2_61 061  trisc2  00006d18  tensix Tensix instruction a1=TTSETADCXX(4, 0xF) old_trisc2_55->old_trisc2_61 tensix_instr old_trisc2_57 057  trisc2  00006d08  tensix Tensix instruction ttwrcfg 28,0,12 | cfg[12] := dma_reg[28] 32b (PCK0_ADDR_CTRL_XY_REG_0) old_trisc2_56->old_trisc2_57 old_trisc2_58 058  trisc2  00006d0c  tensix Tensix instruction ttwrcfg 29,0,13 | cfg[13] := dma_reg[29] 32b (PCK0_ADDR_CTRL_ZW_REG_0) old_trisc2_57->old_trisc2_58 old_trisc2_59 059  trisc2  00006d10  tensix Tensix instruction ttnop old_trisc2_58->old_trisc2_59 old_trisc2_60 060  trisc2  00006d14  tensix Tensix instruction ttnop old_trisc2_59->old_trisc2_60 old_trisc2_60->old_trisc2_61 old_trisc2_61->old_trisc2_62 old_trisc2_66 066  trisc2  00006d44  tensix Tensix instruction a5=TTSETDMAREG(0, 0, 0, 8) old_trisc2_61->old_trisc2_66 tensix_instr old_trisc2_63 063  trisc2  00006d2c  lw add1.TENSIX_PC_BUF_SYNC a5 <- add1.TENSIX_PC_BUF_SYNC (PC_BUF_SYNC) old_trisc2_62->old_trisc2_63 old_trisc2_62->old_trisc2_63 pcbuf:0x4 old_trisc2_63->old_trisc2_64 old_trisc2_65 065  trisc2  00006d38  tensix Tensix instruction ttstallwait 33,8 old_trisc2_64->old_trisc2_65 old_trisc2_96 096  trisc2  00006e94  tensix Tensix instruction a4=TTZEROACC(2, 0, 0, 1) old_trisc2_98 098  trisc2  00006ea0  sw TM.DATA1['dest_offset_id'] a4=0x00000001 old_trisc2_64->old_trisc2_98 old_trisc2_65->old_trisc2_66 old_trisc2_67 067  trisc2  00006d48  tensix Tensix instruction a2=TTSETDMAREG(0, 0x200, 0, 0x10) old_trisc2_66->old_trisc2_67 old_trisc2_66->old_trisc2_67 tensix_instr old_trisc2_68 068  trisc2  00006d4c  tensix Tensix instruction ttstallwait 128,1 old_trisc2_67->old_trisc2_68 old_trisc2_69 069  trisc2  00006d58  tensix Tensix instruction t0=TTWRCFG(4, 1, 0xB4) old_trisc2_67->old_trisc2_69 tensix_instr old_trisc2_68->old_trisc2_69 old_trisc2_70 070  trisc2  00006d5c  tensix Tensix instruction ttdmanop old_trisc2_69->old_trisc2_70 old_trisc2_81 081  trisc2  00006e20  tensix Tensix instruction s8=TTSETADC(4, 0, 3) old_trisc2_69->old_trisc2_81 tensix_instr old_trisc2_71 071  trisc2  00006d60  tensix Tensix instruction ttdmanop old_trisc2_70->old_trisc2_71 old_trisc2_72 072  trisc2  00006d64  tensix Tensix instruction ttsetadcxy 4,0,0,0,0,11 | addr_counter XY ch0=(0,0) ch1=(0,0) mask=0xb old_trisc2_71->old_trisc2_72 old_trisc2_73 073  trisc2  00006d68  tensix Tensix instruction ttsetadczw 4,0,0,0,0,15 | addr_counter ZW ch0=(0,0) ch1=(0,0) mask=0xf old_trisc2_72->old_trisc2_73 old_trisc2_74 074  trisc2  00006d90  lw TriscCB[16].num_pages a1 <- TriscCB[16].num_pages old_trisc2_73->old_trisc2_74 old_trisc2_75 075  trisc2  00006d94  lw TriscCB[16].page_size s10 <- TriscCB[16].page_size old_trisc2_74->old_trisc2_75 old_trisc2_76 076  trisc2  00006d98  lw TriscCB[16].fifo_limit s9 <- TriscCB[16].fifo_limit old_trisc2_75->old_trisc2_76 old_trisc2_77 077  trisc2  00006d9c  lw TriscCB[16].fifo_size s11 <- TriscCB[16].fifo_size old_trisc2_76->old_trisc2_77 old_trisc2_78 078  trisc2  00006da8  lw TriscCB[16].wr_ptr a0 <- TriscCB[16].wr_ptr old_trisc2_77->old_trisc2_78 old_trisc2_78->old_trisc2_79 old_trisc2_79->old_trisc2_80 old_trisc2_80->old_trisc2_81 old_trisc2_82 082  trisc2  00006e2c  tensix Tensix instruction a6=unknown old_trisc2_81->old_trisc2_82 old_trisc2_81->old_trisc2_82 tensix_instr old_trisc2_83 083  trisc2  00006e34  tensix Tensix instruction t1=unknown old_trisc2_82->old_trisc2_83 old_trisc2_82->old_trisc2_83 tensix_instr old_trisc2_84 084  trisc2  00006e38  tensix Tensix instruction ttstallwait 128,9 old_trisc2_83->old_trisc2_84 old_trisc2_86 086  trisc2  00006e44  tensix Tensix instruction a4=unknown old_trisc2_83->old_trisc2_86 tensix_instr old_trisc2_85 085  trisc2  00006e3c  tensix Tensix instruction ttwrcfg 12,0,69 | cfg[69] := dma_reg[12] 32b (THCON_SEC0_REG1_L1_Dest_addr) old_trisc2_84->old_trisc2_85 old_trisc2_85->old_trisc2_86 old_trisc2_87 087  trisc2  00006e48  tensix Tensix instruction ttdmanop old_trisc2_86->old_trisc2_87 old_trisc2_90 090  trisc2  00006e58  tensix Tensix instruction s0=TTSETADCZW(4, 0, 0, 0, 0, 5) old_trisc2_86->old_trisc2_90 tensix_instr old_trisc2_88 088  trisc2  00006e4c  tensix Tensix instruction ttmop 1,0,0 old_trisc2_87->old_trisc2_88 old_trisc2_89 089  trisc2  00006e54  sw TriscCB[16].wr_ptr a0=unknown old_trisc2_88->old_trisc2_89 old_trisc2_89->old_trisc2_90 old_trisc2_91 091  trisc2  00006e68  sw TriscCB[16].wr_ptr a0=unknown old_trisc2_89->old_trisc2_91 old_trisc2_90->old_trisc2_91 old_trisc2_92 092  trisc2  00006e7c  tensix Tensix instruction a4=unknown old_trisc2_90->old_trisc2_92 tensix_instr old_trisc2_91->old_trisc2_92 old_trisc2_93 093  trisc2  00006e84  tensix Tensix instruction ttstallwait 32,8 old_trisc2_92->old_trisc2_93 old_trisc2_94 094  trisc2  00006e88  tensix Tensix instruction t2=TTSTOREREG(0x18, 0x1600A) old_trisc2_92->old_trisc2_94 tensix_instr old_trisc2_93->old_trisc2_94 old_trisc2_95 095  trisc2  00006e8c  tensix Tensix instruction ttstallwait 64,8 old_trisc2_94->old_trisc2_95 old_trisc2_94->old_trisc2_96 tensix_instr old_trisc2_95->old_trisc2_96 old_trisc2_96->old_trisc2_97 old_trisc2_99 099  trisc2  00006eb4  tensix Tensix instruction a6=TTWRCFG(8, 1, 0xB4) old_trisc2_96->old_trisc2_99 tensix_instr old_trisc2_97->old_trisc2_98 old_trisc2_98->old_trisc2_99 old_trisc2_100 100  trisc2  00006eb8  tensix Tensix instruction ttdmanop old_trisc2_99->old_trisc2_100 old_trisc2_101 101  trisc2  00006ebc  tensix Tensix instruction ttdmanop old_trisc2_100->old_trisc2_101 old_ncrisc_1 001  ncrisc  000059b8  lw NOC0.niu_mst_nonposted_wr_req_sent a3 <- NOC0.niu_mst_nonposted_wr_req_sent old_ncrisc_0->old_ncrisc_1 old_ncrisc_2 002  ncrisc  000059bc  lw NOC0.niu_mst_wr_ack_received a3 <- NOC0.niu_mst_wr_ack_received old_ncrisc_1->old_ncrisc_2 old_ncrisc_3 003  ncrisc  000059c4  lw NOC.STATUS_BASE a3 <- NOC.STATUS_BASE old_ncrisc_2->old_ncrisc_3 old_ncrisc_4 004  ncrisc  000059c8  lw NOC0.niu_mst_posted_wr_req_sent a5 <- NOC0.niu_mst_posted_wr_req_sent old_ncrisc_3->old_ncrisc_4 old_ncrisc_5 005  ncrisc  000059d0  lw TensixL1.GO_MSG_INDEX a4 <- TensixL1.GO_MSG_INDEX old_ncrisc_4->old_ncrisc_5 old_ncrisc_5->old_ncrisc_6 old_ncrisc_7 007  ncrisc  00005a48  lw CB.SYNC_TILES_RECEIVED_BASE a0 <- CB.SYNC_TILES_RECEIVED_BASE old_ncrisc_6->old_ncrisc_7 old_ncrisc_8 008  ncrisc  00005a54  lw CB.SYNC_TILES_ACKED_BASE a4 <- CB.SYNC_TILES_ACKED_BASE old_ncrisc_7->old_ncrisc_8 old_ncrisc_9 009  ncrisc  00005a58  lw NcriscCB[0].wr_ptr a5 <- NcriscCB[0].wr_ptr old_ncrisc_8->old_ncrisc_9 old_ncrisc_10 010  ncrisc  00005a94  lw NOC0.noc_cmd_ctrl[buf1] a5 <- NOC0.noc_cmd_ctrl[buf1] old_ncrisc_9->old_ncrisc_10 old_ncrisc_11 011  ncrisc  00005a9c  sw NOC0.noc_ret_addr_lo[buf1] s0=unknown old_ncrisc_10->old_ncrisc_11 old_ncrisc_12 012  ncrisc  00005aa0  sw NOC0.noc_targ_addr_lo[buf1] a4=unknown old_ncrisc_11->old_ncrisc_12 old_ncrisc_13 013  ncrisc  00005aa4  sw NOC0.noc_targ_addr_mid[buf1] zero=0x00000000 old_ncrisc_12->old_ncrisc_13 old_ncrisc_14 014  ncrisc  00005aac  sw NOC0.noc_targ_addr_hi[buf1] a5=unknown old_ncrisc_13->old_ncrisc_14 old_ncrisc_15 015  ncrisc  00005ab0  sw NOC0.noc_at_len_be[buf1] t4=0x00000800 old_ncrisc_14->old_ncrisc_15 old_ncrisc_16 016  ncrisc  00005ab4  sw NOC0.noc_cmd_ctrl[buf1] t0=0x00000001 old_ncrisc_15->old_ncrisc_16 old_ncrisc_17 017  ncrisc  00005ac4  lw NOC0.niu_mst_rd_resp_received a5 <- NOC0.niu_mst_rd_resp_received old_ncrisc_16->old_ncrisc_17 old_ncrisc_18 018  ncrisc  00005ad0  lw CB.SYNC_TILES_RECEIVED_BASE a4 <- CB.SYNC_TILES_RECEIVED_BASE old_ncrisc_17->old_ncrisc_18 old_ncrisc_19 019  ncrisc  00005ad8  lw NcriscCB[0].rd_ptr a5 <- NcriscCB[0].rd_ptr old_ncrisc_18->old_ncrisc_19 old_ncrisc_20 020  ncrisc  00005ae4  lw NcriscCB[0].num_pages a0 <- NcriscCB[0].num_pages old_ncrisc_19->old_ncrisc_20 old_ncrisc_21 021  ncrisc  00005ae8  sw CB.SYNC_TILES_RECEIVED_BASE a4=unknown old_ncrisc_20->old_ncrisc_21 old_ncrisc_22 022  ncrisc  00005af4  lw NcriscCB[0].page_size a4 <- NcriscCB[0].page_size old_ncrisc_21->old_ncrisc_22