ldm layouts

LDM (Local Data Memory) Per-Core Layouts

Overview

Each Tensix tile on Blackhole contains five RISC-V cores: BRISC (data-movement manager), NCRISC (NOC/DRAM data-mover), and three Tensix co-processor cores TRISC0 (unpack), TRISC1 (math), and TRISC2 (pack). Each core has a private SRAM region called Local Data Memory (LDM) that holds per-core state: NOC counters, bank lookup tables, circular-buffer interface descriptors, coordinate variables, and the stack.

All five cores address their LDM at the same virtual base address 0xFFB00000. The hardware memory router silently redirects each core’s accesses to its own physical bank — there is no aliasing between cores. BRISC and NCRISC each have 8 KiB (0xFFB00000–0xFFB01FFF); TRISC0, TRISC1, and TRISC2 each have 4 KiB (0xFFB00000–0xFFB00FFF).

The layouts below are verified against Blackhole-compiled ELFs. Offsets are from the 0xFFB00000 base. Sizes are in bytes. Fields at non-obvious offsets are a consequence of the C/C++ struct layout rules applied by the RISC-V rv32i toolchain (4-byte natural alignment, no padding inserted by the linker script beyond what the compiler produces).

BRISC LDM (8 KiB: 0xFFB00000–0xFFB01FFF)

NCRISC LDM (8 KiB: 0xFFB00000–0xFFB01FFF)

TRISC0 / TRISC2 LDM (Unpack / Pack — 4 KiB: 0xFFB00000–0xFFB00FFF)

TRISC0 (unpack) and TRISC2 (pack) share an identical LDM layout. Both interact with circular buffers, so both carry a full cb_interface[64] array.

TRISC1 LDM (Math — 4 KiB: 0xFFB00000–0xFFB00FFF)

TRISC1 (math) has no CB interface; the math core does not push or pop circular buffer entries directly.

NOC Counter Arrays

Each of the six per-NOC counter variables (noc_reads_num_issued, noc_nonposted_writes_num_issued, noc_nonposted_writes_acked, noc_nonposted_atomics_acked, noc_posted_writes_num_issued) is a uint32_t[NUM_NOCS] array with NUM_NOCS = 2. Total size is 8 bytes. Index 0 corresponds to NOC0 and index 1 to NOC1.

At boot, noc_local_state_init() reads the hardware NOC status-counter registers for each NOC and stores the values into these LDM arrays. Subsequent NOC operations increment the LDM copies; fence and barrier routines poll the hardware registers and compare against the stored values to determine when outstanding transactions are complete.

Emulator note: the emulator must implement these arrays as per-core LDM state, not as shared global state, because each core tracks its own outstanding NOC transactions independently.

CB Interface Array (cb_interface)

The cb_interface[64] array stores the local (fast-path) state for up to 64 circular buffers. Each entry is a LocalCBInterface struct of exactly 32 bytes comprising 8 uint32_t fields:

Blackhole supports 64 CBs (NUM_CIRCULAR_BUFFERS = 64), double the 32-CB limit on Wormhole. The total array size is 64 × 32 = 2048 bytes (0x800). TRISC1 (math) does not carry this array because the math core reads operands from the Dest register file rather than CB L1 addresses.

Bank Lookup Tables

noc_bank_table_init() runs during firmware boot on BRISC and NCRISC. It copies the bank lookup tables from a scratch region in L1 (MEM_BANK_TO_NOC_SCRATCH = 0x0116B0) into the corresponding LDM arrays. The L1 scratch region is pre-populated by the host before the cores are released from reset.

Table dimensions (Blackhole)

dram_bank_to_noc_xy and l1_bank_to_noc_xy

Type: uint16_t[NUM_NOCS][NUM_BANKS]. Each entry encodes a NOC coordinate as a packed 16-bit value:

entry = (noc_y << 6) | noc_x

Both noc_x and noc_y are 6-bit fields. The shift constant 6 matches the Blackhole NOC coordinate width. To decode: x = entry & 0x3F, y = (entry >> 6) & 0x3F.

bank_to_dram_offset and bank_to_l1_offset

Type: uint32_t[NUM_BANKS]. Each entry is the byte offset added to the NOC base address for that bank to produce the canonical address of bank slot 0. Interleaved allocation uses these offsets plus a stride computed at runtime.

Emulator Implementation Notes

The emulator must maintain five separate physical LDM banks, all mapped to the same virtual address 0xFFB00000 from the perspective of each core’s address translation. Memory accesses by a core to 0xFFB00000–0xFFB01FFF (BRISC/NCRISC) or 0xFFB00000–0xFFB00FFF (TRISC0/1/2) must be dispatched to that core’s private bank, never to any other core’s bank.

Before releasing any core from reset, the emulator must pre-populate the L1 scratch region at MEM_BANK_TO_NOC_SCRATCH (0x0116B0) with the correct bank tables for the simulated topology. The firmware’s noc_bank_table_init() routine will copy these into LDM; the emulator does not inject the tables directly into LDM.

The __global_pointer$ symbol at 0x07F0 (relative to LDM base) is the value written to the gp register by the CRT startup code. The emulator must initialize gp to 0xFFB007F0 for all cores at reset so that GP-relative data accesses resolve correctly. Stack pointers initialize to 0xFFB01FF0 (BRISC/NCRISC) or 0xFFB00FF0 (TRISC0/1/2); the low 4 bytes are reserved by the RISC-V ABI red zone.

Source References