sfpu operations

Vector Unit (SFPU) Operations

Overview

The Vector Unit (SFPU) is a 32-lane SIMD unit inside the Tensix coprocessor. Each lane operates on 32-bit values independently. The SFPU is composed of five sub-units that can operate concurrently when SFPLOADMACRO is used, but in the normal case only one sub-unit executes per cycle:

The SFPU clocks at 1.35 GHz on Blackhole A0.

1. LReg Register File

1.1 Register Array

The register file is modelled as:

union { uint32_t u32; int32_t i32; float f32; } LReg[17][32];

The [17] entries are not all uniform. Only LReg[0..7] are general-purpose writable compute registers. The remainder are read-only constants, programmable constants, or special-purpose entries.

1.2 Full Register Map

Hardware-fixed constants (indices 8, 9, 10, 15) are set by silicon and require no initialization.

Programmable constants (indices 11–14) are 32-lane registers that are effectively 8-lane: SFPCONFIG always takes input from the first 8 lanes of LReg[0] and broadcasts them vertically to all 32 lanes. The SFPI compiler initializes LReg[11] to -1.0f at startup. The firmware function ex_load_const() called by BRISC at boot loads any other constants the software stack requires.

1.3 Lane Layout

Each LReg[i] is 32 lanes of 32 bits. For cross-lane operations it is useful to view those 32 lanes as a 4×8 grid (4 rows, 8 columns):

Lane  0  Lane  1  Lane  2  Lane  3  Lane  4  Lane  5  Lane  6  Lane  7   (Row 0)
Lane  8  Lane  9  Lane 10  Lane 11  Lane 12  Lane 13  Lane 14  Lane 15   (Row 1)
Lane 16  Lane 17  Lane 18  Lane 19  Lane 20  Lane 21  Lane 22  Lane 23   (Row 2)
Lane 24  Lane 25  Lane 26  Lane 27  Lane 28  Lane 29  Lane 30  Lane 31   (Row 3)

Instructions that operate purely lanewise (the vast majority) do not care about this layout. Instructions involving cross-lane movement (SFPSHFT2, SFPCONFIG, SFPTRANSP) move data horizontally or vertically within this grid.

1.4 Data Types

Each LReg slot holds 32 bits interpreted as one of:

• FP32: IEEE 754 single precision (1 sign, 8 exponent, 23 mantissa). Denormals are flushed to zero on output from arithmetic; arithmetic treats denormal inputs as zero.
• uint32_t: Unsigned 32-bit integer.
• int32_t: Signed two’s complement 32-bit integer.
• Sign-magnitude int32: 1 sign bit, 31 magnitude bits (same format as Dst Integer “32”). Non-negative values share the same bit pattern across all three integer types.

Software may bitcast freely between any of these types.

2. SFPLOAD / SFPSTORE — Dest ↔ LReg Data Movement

2.1 Dest Addressing

Dest is a 1024×16 array of 16-bit cells (or 512×16 of 32-bit cells in Dst32b mode). SFPLOAD and SFPSTORE operate on a slice of 4 consecutive rows × 8 columns (even or odd) = 32 elements, matching one full LReg.

The effective address Addr is a 10-bit value computed as:

Addr = Imm10 + DEST_TARGET_REG_CFG_MATH_Offset
     + RWCs[Thread].Dst + Config.DEST_REGW_BASE_Base
     + (RWCs[Thread].Sp + Config.DEST_SP_BASE_Base) & 3

(The MOD0_FMT_INT32_ALL mode uses a different formula with the Sp and Dst offsets swapped; it also automatically decrements RWCs.Sp on load and increments it on store.)

The address bits determine:

• Addr[9:2] — selects an aligned group of 4 rows.
• Addr[1] — selects even columns (0) or odd columns (1).
• Addr[0] — unused.

2.2 Lane-to-Dest Mapping

For a given Addr:

def lane_to_dst(addr, lane):
    row    = (addr & ~3) + (lane // 8)   # 4-row group + which row within group
    col    = (lane & 7) * 2              # even column (0, 2, 4, ..., 14)
    if (addr & 2) or DEST_RD_COL_EXCHANGE:
        col += 1                         # odd column instead
    return row, col

A full 16×16 tile in Dest (256 elements) requires 8 SFPLOAD + INCRWC cycles:

SFPLOAD  LReg[x], ..., Addr=0   → loads rows 0-3, even cols → 32 elements
INCRWC   (advances Dst RWC by 1)
SFPLOAD  LReg[x], ..., Addr=0   → loads rows 0-3, odd cols  → 32 elements
INCRWC   (advances Dst RWC by 1)
SFPLOAD  LReg[x], ..., Addr=0   → loads rows 4-7, even cols → 32 elements
...
(8 total SFPLOAD instructions cover the full 16×16 = 256-element tile)

2.3 SFPLOAD Syntax and Mode Table

TT_SFPLOAD(/* u4 */ VD, /* u4 */ Mod0, /* u3 */ AddrMod, /* u10 */ Imm10)

VD must be 0–7 for the instruction to have any effect. AddrMod selects an address modifier from the address modifier table (see pack/unpack-registers.md).

Dst bit-field shuffling: Dst stores FP32 and BF16 with the sign and exponent fields swapped relative to IEEE 754 order. SFPLOAD unshuffles them. SFPSTORE re-shuffles them. The unshuffled form is:

// Dst BF16 storage: Sign,Man(7b),Exp(8b)  →  LReg: Sign,Exp(8b),Man(7b)
// Dst FP32 storage: Sign,ManHi(7b),Exp(8b),ManLo(16b)  →  LReg: Sign,Exp(8b),ManHi(7b),ManLo(16b)

2.4 SFPSTORE Syntax and Mode Table

TT_SFPSTORE(/* u4 */ VD, /* u4 */ Mod0, /* u3 */ AddrMod, /* u10 */ Imm10)

VD can be 0–11 (or 0–7 with DISABLE_BACKDOOR_LOAD false for values 8–11 which write to LoadMacroConfig). The mode table mirrors SFPLOAD but with conversions reversed:

2.5 Instruction Scheduling for SFPLOAD/SFPSTORE

A minimum of 3 unrelated Tensix instructions must execute between a Matrix Unit (FPU) instruction that writes to Dest and an SFPLOAD that reads that same region. If no useful instructions are available, any Tensix NOP works. STALLWAIT with block bit B8 and condition C7 also works but is not recommended.

3. Per-Instruction Semantics

The notation lanewise { ... } means the body executes independently for each of the 32 lanes. LaneEnabled is the per-lane predication result (see Section 4). Instructions that set LaneFlags do so regardless of whether the lane is enabled, unless otherwise noted.

3.1 SFPMAD — Multiply-Add

TT_SFPMAD(/* u4 */ VA, /* u4 */ VB, /* u4 */ VC, /* u4 */ VD, /* u4 */ Mod1)

Latency: 2 cycles. IPC: 1.

Computes VD = ±(VA * VB) ± VC in FP32, lanewise.

def sfpmad(VA, VB, VC, VD, Mod1, LReg):
    for lane in range(32):
        if not lane_enabled(lane): continue
        va = (LReg[7][lane] & 15) if (Mod1 & SFPMAD_MOD1_INDIRECT_VA) else VA
        a = LReg[va][lane]
        b = LReg[VB][lane]
        c = LReg[VC][lane]
        if Mod1 & SFPMAD_MOD1_NEGATE_VA: a ^= 0x80000000
        if Mod1 & SFPMAD_MOD1_NEGATE_VC: c ^= 0x80000000
        d = fma_fp32(a, b, c)  # partially fused, round-to-nearest-even
        vd = (LReg[7][lane] & 15) if ((Mod1 & SFPMAD_MOD1_INDIRECT_VD) and VD != 16) else VD
        if vd < 8 or vd == 16:
            LReg[vd][lane] = d

IEEE 754 notes: Denormal inputs treated as zero. NaN/Inf propagate normally. If a NaN is emitted, it is always the canonical NaN 0x7FC00000. Rounding is round-to-nearest-ties-to-even. Denormal output is flushed to sign-preserved zero.

Auto-stalling: Hardware automatically stalls the next instruction by 1 cycle if it reads a register written by SFPMAD. Exceptions: SFPAND with SFPAND_MOD1_USE_VB, SFPOR with SFPOR_MOD1_USE_VB, SFPIADD (does not detect VD read), SFPSHFT (does not detect VD read), SFPCONFIG (does not detect LReg[0] read), SFPSWAP (does not detect 1st-cycle reads), and certain modes of SFPSHFT2 require manual SFPNOP insertion.

3.2 SFPADD — Floating-Point Add

TT_SFPADD(/* u4 */ VA, /* u4 */ VB, /* u4 */ VC, /* u4 */ VD, /* u4 */ Mod1)

Latency: 2 cycles. IPC: 1.

Semantically identical to SFPMAD. Convention: set VA = 10 (LCONST_1) so the computation is VD = ±(1.0 * VB) ± VC. Shares the same mode table and auto-stalling rules as SFPMAD.

3.3 SFPMUL — Floating-Point Multiply

TT_SFPMUL(/* u4 */ VA, /* u4 */ VB, /* u4 */ VC, /* u4 */ VD, /* u4 */ Mod1)

Latency: 2 cycles. IPC: 1.

Semantically identical to SFPMAD. Convention: set VC = 9 (LCONST_0) so the computation is VD = ±(VA * VB) + 0. To preserve the sign of negative zero products, use SFPMAD_MOD1_NEGATE_VC so the addend is -0 rather than +0. Shares the same mode table and auto-stalling rules as SFPMAD.

3.4 SFPADDI — Add BF16 Immediate

TT_SFPADDI(/* u16 */ Imm16, /* u4 */ VD, /* u4 */ Mod1)

Latency: 2 cycles. IPC: 1.

Computes VD = BF16ToFP32(Imm16) + ±VD. The source register is implicitly VC = VD (the destination is also read as an input).

def bf16_to_fp32(imm16):
    return struct.unpack('f', struct.pack('I', imm16 << 16))[0]

# VD = BF16ToFP32(Imm16) * 1.0 + (±VC_old)
# where VC = VD initially

Supports SFPMAD_MOD1_NEGATE_VC (bit 1) to negate VD before adding, and SFPMAD_MOD1_INDIRECT_VD (bit 3) for indirect destination. Latency and auto-stalling as per SFPMAD.

3.5 SFPMULI — Multiply by BF16 Immediate

TT_SFPMULI(/* u16 */ Imm16, /* u4 */ VD, /* u4 */ Mod1)

Latency: 2 cycles. IPC: 1.

Computes VD = BF16ToFP32(Imm16) * ±VD + 0.0. The embedded + 0.0 means negative zero results become positive zero. Supports SFPMAD_MOD1_NEGATE_VC (bit 1) and SFPMAD_MOD1_INDIRECT_VD (bit 3). Latency and auto-stalling as per SFPMAD.

BF16-to-FP32 conversion: The 16-bit immediate is interpreted as a BF16 value and expanded to FP32 by appending 16 zero bits in the low position. That is, BF16ToFP32(x) = bitcast<float>(x << 16). There is no rounding, no denormal handling — it is a pure bit-position shift.

3.6 SFPDIVP2 — Adjust FP32 Exponent

TT_SFPDIVP2(/* u8 */ Imm8, /* u4 */ VC, /* u4 */ VD, /* u4 */ Mod1)

Latency: 1 cycle. IPC: 1.

Adjusts the 8-bit exponent field of a FP32 value, leaving sign and mantissa unchanged.

def sfpdivp2(Imm8, VC, VD, Mod1, LReg):
    for lane in range(32):
        if not lane_enabled(lane): continue
        c = LReg[VC][lane]
        Sign = c >> 31
        Exp  = (c >> 23) & 0xFF
        Man  = c & 0x7FFFFF
        if Mod1 & SFPDIVP2_MOD1_ADD:
            if Exp == 255:
                pass  # Inf and NaN left unchanged
            else:
                Exp = (Exp + Imm8) & 0xFF  # wrapping 8-bit addition
        else:
            Exp = Imm8  # replace exponent
        LReg[VD][lane] = (Sign << 31) | (Exp << 23) | Man

Exponent wrapping: When adding, the 8-bit addition wraps around modulo 256. Infinity and NaN (exponent = 255) are left unchanged when adding. Use SFPMULI instead if saturation behavior is needed.

3.7 SFPEXEXP — Extract FP32 Exponent

TT_SFPEXEXP(0, /* u4 */ VC, /* u4 */ VD, /* u4 */ Mod1)

Latency: 1 cycle. IPC: 1.

Extracts the 8-bit exponent field of FP32 and deposits it as a 32-bit integer, optionally subtracting the bias 127.

def sfpexexp(VC, VD, Mod1, LReg):
    Bias = 0 if (Mod1 & SFPEXEXP_MOD1_NODEBIAS) else 127
    for lane in range(32):
        if not lane_enabled(lane): continue
        Exp = (LReg[VC][lane] >> 23) & 0xFF
        LReg[VD][lane] = Exp - Bias  # two's complement integer result
        if VD < 8:
            if Mod1 & SFPEXEXP_MOD1_SET_CC_SGN_EXP:
                LaneFlags[lane] = (LReg[VD][lane] < 0)
            if Mod1 & SFPEXEXP_MOD1_SET_CC_COMP_EXP:
                LaneFlags[lane] = not LaneFlags[lane]

With bias removal (default, NODEBIAS clear): result is in the range -127 (denormal/zero) through +128 (NaN/Inf), as a two’s complement int32_t.

Without bias removal (NODEBIAS set): result is the raw biased exponent 0–255 as a uint32_t.

3.8 SFPEXMAN — Extract FP32 Mantissa

TT_SFPEXMAN(0, /* u4 */ VC, /* u4 */ VD, /* u4 */ Mod1)

Latency: 1 cycle. IPC: 1.

Extracts the 23-bit mantissa field, deposits it in bits [22:0], and sets bit 23 to either 0 or 1.

def sfpexman(VC, VD, Mod1, LReg):
    HiddenBit = 0 if (Mod1 & SFPEXMAN_MOD1_PAD9) else (1 << 23)
    for lane in range(32):
        if not lane_enabled(lane): continue
        Man = LReg[VC][lane] & 0x7FFFFF
        LReg[VD][lane] = HiddenBit + Man

Bits [31:24] are always zero in the result.

3.9 SFPIADD — Integer Add/Subtract

TT_SFPIADD(/* i12 */ (Imm12 & 0xFFF), /* u4 */ VC, /* u4 */ VD, /* u4 */ Mod1)

Latency: 1 cycle. IPC: 1.

Performs integer addition or subtraction. The result is written to VD. Lane flags may optionally be set based on the sign of the result.

def sfpiadd(Imm12, VC, VD, Mod1, LReg):
    VB = VD  # destination also acts as second source in reg-reg mode
    for lane in range(32):
        if not lane_enabled(lane): continue
        if Mod1 & SFPIADD_MOD1_ARG_IMM:
            LReg[VD][lane] = LReg[VC][lane] + sign_extend_12(Imm12)
        elif Mod1 & SFPIADD_MOD1_ARG_2SCOMP_LREG_DST:
            LReg[VD][lane] = LReg[VC][lane] - LReg[VB][lane]
        else:
            LReg[VD][lane] = LReg[VC][lane] + LReg[VB][lane]
        # Truncate to 32 bits (unsigned wrapping)
        LReg[VD][lane] &= 0xFFFFFFFF
        if VD < 8:
            if not (Mod1 & SFPIADD_MOD1_CC_NONE):
                LaneFlags[lane] = (as_signed_32(LReg[VD][lane]) < 0)
            if Mod1 & SFPIADD_MOD1_CC_GTE0:
                LaneFlags[lane] = not LaneFlags[lane]

Note: the CC_NONE and CC_GTE0 bits can combine with the ARG_* bits. The Imm12 field is sign-extended to 32 bits.

Hardware bug: The auto-stalling logic does not detect that SFPIADD reads VD. If a preceding 2-cycle instruction (SFPMAD etc.) writes to VD, software must insert a manual SFPNOP.

3.10 SFPSETCC — Set Condition Codes

TT_SFPSETCC(/* u1 */ Imm1, /* u4 */ VC, /* u4 */ VD, /* u4 */ Mod1)

Latency: 1 cycle. IPC: 1.

Sets LaneFlags per lane based on a comparison of VC against zero, or from an immediate bit, or clears it.

def sfpsetcc(Imm1, VC, VD, Mod1, LReg):
    for lane in range(32):
        if not lane_enabled(lane): continue
        if not UseLaneFlagsForLaneEnable[lane]:
            LaneFlags[lane] = False
        elif Mod1 & SFPSETCC_MOD1_CLEAR:
            LaneFlags[lane] = False
        elif Mod1 & SFPSETCC_MOD1_IMM_BIT0:
            LaneFlags[lane] = bool(Imm1)
        else:
            c = as_signed_32(LReg[VC][lane])
            if   (Mod1 & 7) == SFPSETCC_MOD1_LREG_LT0:  LaneFlags[lane] = (c < 0)
            elif (Mod1 & 7) == SFPSETCC_MOD1_LREG_NE0:  LaneFlags[lane] = (c != 0)
            elif (Mod1 & 7) == SFPSETCC_MOD1_LREG_GTE0: LaneFlags[lane] = (c >= 0)
            elif (Mod1 & 7) == SFPSETCC_MOD1_LREG_EQ0:  LaneFlags[lane] = (c == 0)

Note on FP32 values: FP32 sign bit is at bit 31, same position as integer sign, so LREG_LT0 tests the FP32 sign bit directly. However, negative zero (0x80000000) and NaN have sign bit set even though they are not “less than zero” in the IEEE sense. Software should flush negative zero before using SFPSETCC on FP32 data.

3.11 SFPMOV — Vector Register Move

TT_SFPMOV(0, /* u4 */ VC, /* u4 */ VD, /* u4 */ Mod1)

Latency: 1 cycle. IPC: 1.

Moves data from VC to VD, with optional negation, all-lanes-enabled override, or special source selection.

def sfpmov(VC, VD, Mod1, LReg):
    for lane in range(32):
        if not (lane_enabled(lane) or (Mod1 == SFPMOV_MOD1_ALL_LANES_ENABLED)):
            continue
        if Mod1 & SFPMOV_MOD1_FROM_SPECIAL:
            # VC selects which configuration register to read
            if   VC in (0,1,2,3): x = LoadMacroConfig[lane].InstructionTemplate[VC]
            elif VC in (4,5,6,7): x = LoadMacroConfig[lane].Sequence[VC-4]
            elif VC == 8:         x = LoadMacroConfig[lane].Misc
            elif VC == 9:         x = advance_prng(lane)
            elif VC == 15:        x = LaneConfig[lane]
            else:                 x = 0
        else:
            x = LReg[VC][lane]
            if Mod1 & SFPMOV_MOD1_NEGATE:
                x ^= 0x80000000  # flip sign bit (FP32 or sign-magnitude)
        if VD < 8 or VD == 16:
            LReg[VD][lane] = x

When SFPMOV_MOD1_FROM_SPECIAL with VC = 9: advances the per-lane PRNG and returns the previous state (useful for seeding or reading random bits directly).

3.12 SFPLUTFP32 — Piecewise Linear LUT Evaluation

TT_SFPLUTFP32(/* u4 */ VD, /* u4 */ Mod1)

Latency: 2 cycles. IPC: 1.

Evaluates a piecewise linear function of Abs(LReg[3]). The input is always taken from LReg[3]. The piece is selected by comparing the magnitude against fixed breakpoints. All computations use the FP32 MAD unit.

Piece index selection:

def select_piece(b):
    # b = abs(LReg[3][lane])
    if b < 1.0:  return 0  # LReg[0] / LReg[4]
    if b < 2.0:  return 1  # LReg[1] / LReg[5]
    return 2               # LReg[2] / LReg[6]

The four table modes:

Additional modifier bits:

Lut16ToFp32 conversion: The 16-bit FP16-like values are decoded as (1 + Man/2^10) * 2^(Exp-15). Crucially, exponent 31 (which would be Inf/NaN in IEEE FP16) maps to +0 or -0 instead, and exponent 0 (which would be denormal in IEEE FP16) is treated as a normalized number.

Computation: d = a * Abs(LReg[3]) + c, with MAD semantics as per SFPMAD.

3.13 SFPSTOCHRND — Stochastic Rounding

This instruction has three distinct flavors selected by Mod1:

TT_SFP_STOCH_RND(/* u2 */ RoundingMode, 0, /* u4 */ VC, /* u4 */ VC, /* u4 */ VD, /* u3 */ Mod1)

Note: VC appears twice to work around a false-dependency bug in the auto-stalling logic. In the encoding, set VB = VC.

Latency: 1 cycle. IPC: 1. Sub-unit: Round.

Rounding Mode Field

Known hardware bugs in stochastic mode: Slight bias toward increasing magnitude (comparison uses >= instead of >), and can increase magnitude of values that don’t require rounding.

Flavor A: FP32 → Reduced-precision FP32

Result is FP32 with reduced mantissa precision, suitable for lossless SFPSTORE MOD0_FMT_FP16A or MOD0_FMT_BF16.

Special cases: denormals → +0; negative zero → +0; -NaN → -Inf; +NaN → +Inf.

Flavor B: FP32 → Bounded Sign-Magnitude Integer

Input |x| < 0.5 always rounds to zero (even in stochastic mode — bug). Input |x| ≥ 2^16 or NaN clamps to MaxMagnitude.

Flavor C: Sign-Magnitude Integer → Reduced-range Sign-Magnitude Integer

The magnitude is shifted right by Imm5 (or by VB & 31 if UseImm5 is false). Discarded bits are used for rounding against PRNG. This is the integer equivalent of Flavor A.

3.14 SFPCAST — Type Conversion

TT_SFPCAST(/* u4 */ VC, /* u4 */ VD, /* u4 */ Mod1)

Latency: 1 cycle. IPC: 1.

Modes 0 and 1 — SM32 to FP32: Exact for |x| ≤ 2^24. Larger values are rounded. The conversion uses lzcnt of the magnitude to find the leading 1 bit and builds an FP32 result.

Mode 3 — format conversion: The hardware computes Sign | (Sign ? -c : c) which converts two’s complement to sign-magnitude and sign-magnitude to two’s complement identically.

3.15 SFPABS — Absolute Value

TT_SFPABS(0, /* u4 */ VC, /* u4 */ VD, /* u4 */ Mod1)

Latency: 1 cycle. IPC: 1.

For sign-magnitude integer absolute value (which also works for FP32 without NaN exception handling), use SFPSETSGN with SFPSETSGN_MOD1_ARG_IMM and Imm1 = 0.

3.16 SFPAND, SFPOR, SFPXOR, SFPNOT — Bitwise Logic

All operate lanewise on 32-bit values, respecting LaneEnabled. Latency: 1 cycle.

SFPAND:

TT_SFPAND(/* u4 */ VB, /* u4 */ VC, /* u4 */ VD, /* u4 */ Mod1)

• Mod1 = 0: VD = VD & VC
• Mod1 = 1 (SFPAND_MOD1_USE_VB): VD = VB & VC

Hardware bug: auto-stalling logic ignores SFPAND_MOD1_USE_VB and thinks VD is always the second operand.

SFPOR:

TT_SFPOR(/* u4 */ VB, /* u4 */ VC, /* u4 */ VD, /* u4 */ Mod1)

• Mod1 = 0: VD = VD | VC
• Mod1 = 1 (SFPOR_MOD1_USE_VB): VD = VB | VC

Hardware bug: same as SFPAND.

SFPXOR:

TT_SFPXOR(0, /* u4 */ VC, /* u4 */ VD, 0)

• Always: VD = VD ^ VC (destination is also second source)

SFPNOT:

TT_SFPNOT(0, /* u4 */ VC, /* u4 */ VD, 0)

• Always: VD = ~VC (bitwise NOT)

3.17 SFPLZ — Count Leading Zeros

TT_SFPLZ(0, /* u4 */ VC, /* u4 */ VD, /* u4 */ Mod1)

Latency: 1 cycle. IPC: 1.

Counts leading zero bits in VC. Optionally masks the sign bit first (for sign-magnitude integers). Also optionally sets LaneFlags based on whether VC was zero.

def sfplz(VC, VD, Mod1, LReg):
    for lane in range(32):
        if not lane_enabled(lane): continue
        c = LReg[VC][lane]
        if Mod1 & SFPLZ_MOD1_NOSGN_MASK:
            c &= 0x7FFFFFFF  # mask sign bit
        LReg[VD][lane] = count_leading_zeros_32(c)  # 32 if c == 0
        if VD < 8:
            if Mod1 & SFPLZ_MOD1_CC_NE0:
                LaneFlags[lane] = (c != 0)
            if Mod1 & SFPLZ_MOD1_CC_COMP:
                LaneFlags[lane] = not LaneFlags[lane]

3.18 SFPSETEXP — Set FP32 Exponent

TT_SFPSETEXP(/* u8 */ Imm8, /* u4 */ VC, /* u4 */ VD, /* u4 */ Mod1)

Latency: 1 cycle. IPC: 1.

Combines sign and mantissa from VC with an exponent from one of three sources:

Result: {VC.Sign, new_exp, VC.Man} — sign and mantissa from VC, exponent from selected source.

3.19 SFPSETSGN — Set FP32 Sign Bit

TT_SFPSETSGN(/* u1 */ Imm1, /* u4 */ VC, /* u4 */ VD, /* u4 */ Mod1)

Latency: 1 cycle. IPC: 1.

Combines exponent and mantissa from VC with a sign bit from one of two sources:

Result: {new_sign, VC.Exp, VC.Man}.

Use cases:

• Imm1 = 0, Mod1 = 1: VD = Abs(VC) (clear sign bit — for FP32 or sign-magnitude)
• Imm1 = 1, Mod1 = 1: VD = -Abs(VC) (force negative)

3.20 SFPGT — Greater-Than Comparison

TT_SFPGT(0, /* u4 */ VC, /* u4 */ VD, /* u4 */ Mod1)

Latency: 1 cycle. IPC: 1. New in Blackhole.

Tests VD > VC (where VB = VD internally). The comparison uses sign-magnitude ordering, which is equivalent to IEEE 754 total order for FP32 (treating -NaN < -Inf < … < -0 < +0 < … < +Inf < +NaN).

The result can be written to three destinations simultaneously:

SFPLE is the exact inverse: tests VD <= VC.

3.21 SFPARECIP — Approximate Reciprocal or Exponential

TT_SFPARECIP(/* u4 */ VB, /* u4 */ VC, /* u4 */ VD, /* u4 */ Mod1)

Latency: 1 cycle. IPC: 1. New in Blackhole.

Accuracy:

• ApproxRecip(x): for 2^-126 ≤ x < 2^126, error bound is 0.9944 / x < result < 1.0054 / x. At x = 1.0, gives 0.99609375.
• ApproxExp(x): for 0 ≤ x < 2, error bound is 0.9922 * e^x < result < 1.016 * e^x. For x ≥ 2, result is not useful.

Both functions use a hardware lookup table (128 entries for reciprocal, 896 entries for exponential). The sign removal-and-restore means SFPARECIP_MOD1_RECIP computes sign(VC) / |VC| and SFPARECIP_MOD1_EXP computes sign(VC) * e^|VC|, which is not the usual mathematical definition.

3.22 SFPSWAP — Swap, Min+Max

TT_SFPSWAP(0, /* u4 */ VC, /* u4 */ VD, /* u4 */ Mod1)

Latency: 2 cycles. IPC: ≤1.

Conditionally or unconditionally swaps the contents of VC and VD.

Comparison uses sign-magnitude ordering (identical to SFPGT). When LaneConfig.ENABLE_DEST_INDEX is true, performs argmin+argmax across LReg[0..3] and LReg[4..7] simultaneously.

Scheduling: Hardware auto-stalls the next instruction by 1 cycle after SFPSWAP. If software inserts an explicit SFPNOP, the SFPSWAP + SFPNOP pair takes 2 cycles total rather than 3. Hardware bug: auto-stalling does not detect 1st-cycle reads of VC and VD.

3.23 SFPSHFT — Bitwise Shift

TT_SFPSHFT(/* i12 */ (Imm12 & 0xFFF), /* u4 */ VC, /* u4 */ VD, /* u4 */ Mod1)

Latency: 1 cycle. IPC: 1.

Shifts VD (or VC if SFPSHFT_MOD1_ARG_IMM_USE_VC is set) by a signed shift amount.

def sfpshft(Imm12, VC, VD, Mod1, LReg):
    VB = VD  # second source
    for lane in range(32):
        if not lane_enabled(lane): continue
        x = LReg[VB][lane]
        shift = as_signed_32(LReg[VC][lane])
        if Mod1 & SFPSHFT_MOD1_ARG_IMM:
            if Mod1 & SFPSHFT_MOD1_ARG_IMM_USE_VC:
                x = LReg[VC][lane]
            shift = sign_extend_12(Imm12)
        if shift >= 0:
            LReg[VD][lane] = x << (shift & 31)
        elif Mod1 & SFPSHFT_MOD1_ARITHMETIC:
            LReg[VD][lane] = as_signed_32(x) >> ((-shift) & 31)
        else:
            LReg[VD][lane] = x >> ((-shift) & 31)

Hardware bug: auto-stalling does not detect that SFPSHFT reads VD.

3.24 SFPSHFT2 — Vector Shuffle or Bitwise Shift

TT_SFPSHFT2(/* u4 */ VB, /* u4 */ VC, /* u4 */ VD, /* u4 */ Mod1)

Latency: 1 or 2 cycles (see table). Sub-unit: Round.

Performs cross-lane shuffles of LReg[0..3] or bitwise shifts.

Scheduling: Modes 2, 3, 4 require the next instruction to be SFPNOP (auto-stall applies, but explicit NOP makes the pair cost 2 cycles instead of 3).

Hardware bugs: auto-stalling does not detect reads for modes 2–4, and thinks modes 5–6 read from VD instead of VB.

3.25 SFPMUL24 — 23-bit Integer Multiply

TT_SFPMUL24(/* u4 */ VA, /* u4 */ VB, /* u4 */ VC, /* u4 */ VD, /* u4 */ Mod1)

Latency: 2 cycles. IPC: 1. New in Blackhole.

Multiplies two 23-bit integers (the low 23 bits of VA and VB), returning either the low or high 23 bits of the 46-bit product.

Important: Always set VC = 9 (LCONST_0). If VC is non-zero, a non-contractual shift/add adjustment is applied to the result via reuse of the FP32 datapath.

Latency and auto-stalling rules are the same as SFPMAD.

3.26 SFPSETMAN — Set FP32 Mantissa

TT_SFPSETMAN(/* u12 */ Imm12, /* u4 */ VC, /* u4 */ VD, /* u4 */ Mod1)

Latency: 1 cycle. IPC: 1.

3.27 SFPLOADI — Load Immediate

TT_SFPLOADI(/* u4 */ VD, /* u4 */ Mod0, /* u16 */ Imm16)

Latency: 1 cycle. IPC: 1. Sub-unit: Load.

Writes a 16-bit or 32-bit constant to all lanes of VD (must be 0–7). Does not affect the programmable constant registers (LReg[11..14]); use SFPCONFIG for those.

To write an arbitrary 32-bit value, use SFPLOADI_MOD0_UPPER followed by SFPLOADI_MOD0_LOWER.

3.28 SFPCONFIG — Write Configuration / Programmable Constants

TT_SFPCONFIG(/* u16 */ Imm16, /* u4 */ VD, /* u4 */ Mod1)

Latency: ≤2 cycles. IPC: 1.

Writes to LReg[11..14] (programmable constants), LaneConfig, or LoadMacroConfig. Input always comes from the first 8 lanes of LReg[0] (broadcast to all 32 lanes), or from Imm16 when MOD1_IMM16_IS_VALUE is set.

VD destination selector:

Scheduling: If SFPCONFIG changes LaneConfig.DISABLE_BACKDOOR_LOAD, insert an SFPNOP immediately after to ensure the new value is seen by the next SFPU instruction.

3.29 SFPNOP — No Operation

TTI_SFPNOP

Latency: 1 cycle. IPC: 1. Sub-unit: Load (or whichever sub-unit SFPLOADMACRO schedules it on).

Occupies the Vector Unit for one cycle with no observable effect. Used to fill dependency gaps.

4. SIMT Predication

The SFPU implements per-lane conditional execution through a two-level system: per-lane LaneFlags booleans and a stack-based scope mechanism.

4.1 Predication State

// Per-lane state (32 independent instances):
bool LaneFlags[32];                    // current condition flag
bool UseLaneFlagsForLaneEnable[32];    // is predication active?

struct FlagStackEntry {
    bool LaneFlags;
    bool UseLaneFlagsForLaneEnable;
};
Stack<FlagStackEntry> FlagStack[32];   // depth limit: 8 entries

LaneFlags and UseLaneFlagsForLaneEnable both initialize to false.

4.2 Lane Enable Logic

def is_lane_enabled(lane):
    # ROW_MASK in LaneConfig always takes priority
    if LaneConfig[lane & 7].ROW_MASK.bit[lane // 8]:
        return False
    # Then per-lane flag predication
    if UseLaneFlagsForLaneEnable[lane]:
        return LaneFlags[lane]
    # Otherwise all lanes enabled
    return True

When UseLaneFlagsForLaneEnable is false (the initial state), all lanes execute every instruction (subject only to ROW_MASK). Once set to true by SFPENCC, LaneFlags gates every instruction write.

4.3 Effect of Predication

When a lane is disabled (LaneEnabled = false):

• The lane’s LReg entries are not written — they preserve their previous values.
• The lane’s LaneFlags state is still updated by comparison instructions (SFPSETCC, SFPGT, SFPLE, SFPLZ, SFPIADD, SFPEXEXP) because these must set the flag for disabled lanes too (otherwise the lane could never re-enable itself).

4.4 SFPENCC — Enable Conditional Execution

TT_SFPENCC(/* u2 */ Imm2, 0, /* u4 */ VD, /* u4 */ Mod1)

Controls UseLaneFlagsForLaneEnable and optionally sets LaneFlags.

def sfpencc(Imm2, VD, Mod1):
    for lane in range(32):
        if not lane_enabled(lane): continue
        if Mod1 & SFPENCC_MOD1_EI:
            UseLaneFlagsForLaneEnable[lane] = bool(Imm2 & SFPENCC_IMM2_E)
        elif Mod1 & SFPENCC_MOD1_EC:
            UseLaneFlagsForLaneEnable[lane] = not UseLaneFlagsForLaneEnable[lane]
        # else: leave UseLaneFlagsForLaneEnable unchanged

        if Mod1 & SFPENCC_MOD1_RI:
            LaneFlags[lane] = bool(Imm2 & SFPENCC_IMM2_R)
        else:
            LaneFlags[lane] = True

Common pattern to enable predication:

TT_SFPENCC(3, 0, VD, SFPENCC_MOD1_EI_RI);  // Imm2=3: enable=1, flags=1 → all lanes active

4.5 SFPPUSHC — Push Condition Stack

TT_SFPPUSHC(0, 0, /* u4 */ VD, /* u4 */ Mod1)

Stack depth limit: 8.

• Mod1 = 0: Push — copies current {LaneFlags, UseLaneFlagsForLaneEnable} onto the stack. Stack must not be full.
• Mod1 = 1..12: Mutate top — does not push; instead replaces the top’s UseLaneFlagsForLaneEnable with current and applies a boolean operation to the top’s LaneFlags (see BooleanOp table below).
• Mod1 = 13: Inverts current LaneFlags, then replaces stack top with inverted state.
• Mod1 = 14: Replaces stack top with {true, true}.
• Mod1 = 15: Replaces stack top with {true, false}.

4.6 SFPPOPC — Pop Condition Stack

TT_SFPPOPC(0, 0, /* u4 */ VD, /* u4 */ Mod1)

• Mod1 = 0: Pop — restores LaneFlags and UseLaneFlagsForLaneEnable from the top of stack. Stack must not be empty.
• Mod1 = 1..12: Peek and mutate — does not pop; reads top of stack and applies a boolean operation to current LaneFlags.
• Mod1 = 13: Inverts current LaneFlags (no stack access).
• Mod1 = 14: Sets {UseLaneFlagsForLaneEnable = true, LaneFlags = true}.
• Mod1 = 15: Sets {UseLaneFlagsForLaneEnable = true, LaneFlags = false}.

4.7 SFPCOMPC — Complement (Implement else)

TT_SFPCOMPC(0, 0, /* u4 */ VD, 0)

Implements the else branch of a SIMT if/else. Uses the top of the flag stack to determine which lanes were active in the if branch, then sets LaneFlags to select only those lanes that were not active during if.

def sfpcompc(VD):
    for lane in range(32):
        if not lane_enabled_or_backdoor(lane, VD): continue
        Top = FlagStack[lane].top() if not FlagStack[lane].empty() else {True, True}
        if Top.UseLaneFlagsForLaneEnable and UseLaneFlagsForLaneEnable[lane]:
            LaneFlags[lane] = Top.LaneFlags and not LaneFlags[lane]
        else:
            LaneFlags[lane] = False

4.8 BooleanOp Table (used by SFPPUSHC / SFPPOPC with Mod1 1..12)

Let A = existing top-of-stack LaneFlags, B = current LaneFlags:

4.9 SIMT if/else/endif Pattern

// Idiomatic SIMT branching (compiler convention):
SFPENCC  3, VD, EI_RI       // enable predication, all lanes start active
SFPPUSHC 0, VD, 0           // push initial state onto stack
// --- condition setup: sets LaneFlags to select "if" lanes ---
SFPSETCC ...                 // or SFPGT, SFPIADD, etc.
// --- if body: only lanes with LaneFlags=true execute ---
<instructions>
SFPCOMPC 0, VD, 0           // flip to "else" lanes
// --- else body ---
<instructions>
SFPPOPC  0, VD, 0           // restore flags from before the if

5. Pipeline and Latency

5.1 Instruction Latency Summary

5.2 Dependency Handling

The SFPU implements automatic stalling for most 2-cycle instructions: if the instruction immediately following reads a register written by the 2-cycle instruction, hardware inserts a 1-cycle bubble automatically. This covers SFPMAD, SFPADD, SFPMUL, SFPADDI, SFPMULI, SFPLUTFP32, SFPMUL24, SFPSWAP, and the slower modes of SFPSHFT2.

Exceptions requiring manual SFPNOP insertion (hardware bug — auto-stalling does not detect):

1. SFPAND with SFPAND_MOD1_USE_VB reading a VB written by 2-cycle instruction
2. SFPOR with SFPOR_MOD1_USE_VB reading a VB written by 2-cycle instruction
3. SFPIADD reading VD (the implicit second source) written by 2-cycle instruction
4. SFPSHFT reading VD (the implicit second source) written by 2-cycle instruction
5. SFPCONFIG reading LReg[0] written by 2-cycle instruction
6. SFPSWAP (all modes except SFPSWAP_MOD1_SWAP) reading VC or VD on the 1st cycle

SFPLOADMACRO caution: None of the auto-stalling applies to instructions executed as part of an SFPLOADMACRO sequence. Software is entirely responsible for correct scheduling within those sequences.

5.3 SFPU ↔ FPU (Matrix Unit) Ordering

Reading Dest after the Matrix Unit has written it requires a gap before SFPLOAD:

• Minimum 3 unrelated Tensix instructions between the FPU write and the SFPLOAD.
• Alternatively, STALLWAIT with block bit B8 and condition C7.
• The 3-instruction gap is preferred in practice; STALLWAIT is a fallback.

Writing Dest from the SFPU (SFPSTORE) and then reading it with the FPU similarly requires ordering (handled by the same STALLWAIT mechanisms described in tensix-coprocessor-pipeline.md).

5.4 PRNG

The hardware PRNG used by SFPSTOCHRND and SFPMOV_MOD1_FROM_SPECIAL (VC=9) is a per-lane 32-bit LFSR:

def advance_prng(lane, State):
    result = State[lane]
    taps = popcount(result & 0x80200003)
    State[lane] = ((~taps & 1) << 31) | (result >> 1)
    return result

The statistical quality of this PRNG is poor. Software requiring high-quality randomness should implement its own PRNG in LRegs.

6. Emulator Implementation Notes

6.1 Register File Initialization

At reset:

# Hardware-fixed read-only constants — initialize once at reset
LReg[8]  = [0x3F566189] * 32   # 0.8373f
LReg[9]  = [0x00000000] * 32   # 0.0
LReg[10] = [0x3F800000] * 32   # 1.0f
LReg[15] = [i * 2 for i in range(32)]  # 0, 2, 4, ..., 62

# PRNG state — arbitrary initial value (firmware sets this before use)
PRNG_State = [0] * 32

# Predication state
LaneFlags                = [False] * 32
UseLaneFlagsForLaneEnable = [False] * 32
FlagStack                = [[] for _ in range(32)]  # max depth 8

# LaneConfig — all zero by default
LaneConfig = [0] * 32  # 18-bit field per lane

The programmable constants LReg[11..14] are written by firmware (typically via SFPCONFIG in ex_load_const() called at boot by BRISC). The emulator should not assume any particular value at reset; wait for the SFPCONFIG instruction to write them.

6.2 LReg Write Guards

Only LReg[0..7] and LReg[16] are writable by regular instructions. Write to indices 8–10, 15 must be silently ignored (read-only hardware). Write to indices 11–14 must be rejected unless the instruction is SFPCONFIG.

6.3 FP32 Conformance

The SFPU is “closer to” but not fully IEEE 754 compliant. Key deviations:

• Denormal inputs to arithmetic operations are treated as zero (flush-to-zero input).
• Denormal results are flushed to sign-preserved zero.
• Canonical NaN output is always 0x7FC00000 regardless of input NaN payload.
• The FMA (SFPMAD) is partially fused: the product is kept in higher precision than FP32 but not infinite precision.
• Rounding mode is always round-to-nearest-ties-to-even (for arithmetic); there is no way to change it per-instruction.

6.4 Instruction Dispatch by Sub-unit

In the emulator, each SFPU instruction maps to a specific sub-unit for latency modeling:

LOAD_SUBUNIT  = {"SFPLOAD", "SFPLOADI", "SFPNOP"}
SIMPLE_SUBUNIT = {"SFPMOV", "SFPABS", "SFPAND", "SFPOR", "SFPXOR", "SFPNOT",
                  "SFPSHFT", "SFPLZ", "SFPEXEXP", "SFPEXMAN", "SFPDIVP2",
                  "SFPSETEXP", "SFPSETSGN", "SFPSETMAN", "SFPIADD",
                  "SFPCAST", "SFPSETCC", "SFPENCC", "SFPPUSHC", "SFPPOPC",
                  "SFPCOMPC", "SFPARECIP", "SFPGT", "SFPLE", "SFPCONFIG"}
MAD_SUBUNIT   = {"SFPMAD", "SFPADD", "SFPMUL", "SFPADDI", "SFPMULI",
                  "SFPLUTFP32", "SFPMUL24", "SFPSWAP"}
ROUND_SUBUNIT = {"SFPSTOCHRND", "SFPSHFT2"}
STORE_SUBUNIT = {"SFPSTORE"}

Source References